HYB18M1G16 Datasheet, PDF (24/65 Pages) Qimonda AG – 1-Gbit x16 DDR Mobile-RAM

Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
Parameter
Symbol
-6
- 7.5
Unit Note
min.
max.
min.
max.
ACTIVE to READ or WRITE delay
t_RCD
18
–
22.5
–
ns
6)
PRECHARGE command period
t_RP
18
–
22.5
–
ns
6)
1) The output timing reference level is V_DDQ/2.
2) Parameters t_AC and t_QH are specified for full drive strength and a reference load of 20pF. This reference load is not intended to be either a
precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. For half drive
strength with a nominal load of 10pF parameters t_AC and t_QH are expected to be in the same range. However, these parameters are not
subject to production test but are estimated by device characterization. Use of IBIS or other simulation tools for system validation is
suggested.
3) t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
4)t_DQSQ consists of data ball skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any
given cycle.
5) t_QH = t_HP - t_QHS, where t_HP = minimum half clock period for any given cycle and is defined by clock high or clock low (t_CL, t_CH).t_QHS accounts
for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one transition followed by the worst
case pull-in of DQ on the next transition, both of which are, separately, due to data ball skew and output pattern effects, and p-channel to
n-channel variation of the output drivers.
6) These parameters account for the number of clock cycles and depend on the operating frequency, as follows:
no. of clock cycles = specified delay / clock period; round to the next higher integer.
During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency
after the READ command.
The diagrams in Figure 14 show general timing for each supported CAS latency setting. DQS is driven by the DDR Mobile-
RAM along with output data. The initial low state on DQS is known as the read preamble; the low state coincident with the last
data-out element is known as the read postamble.
Upon completion of a burst, assuming no other READ commands have been initiated, the DQs will go High-Z.
FIGURE 14
READ Burst
CK
CK
Command
Address
READ
BA,Col n
DQS
NOP
CL=2
NOP
NOP
NOP
NOP
DQ
DO n
DQS
DQ
CL=3
DO n
DO n = Data Out from column n
= Don't Care
BA, Col n = Bank A, Column n
Burst Length = 4; 3 subsequent elements of Data Out appear in the programmed order following DO n
Rev.1.0, 2007-03
24
10242006-Y557-TZXW