HYB18M1G16 Datasheet, PDF (12/65 Pages) Qimonda AG – 1-Gbit x16 DDR Mobile-RAM

Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
2.2.1.2 Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type
and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the
starting column address, as shown in Table 5.
2.2.1.3 Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a READ command and the
availability of the first piece of output data. The latency can be programmed to 2 or 3 clocks.
If a READ command is registered and the latency is 3 clocks, the first data element will be valid after (2 * t_CK + t_AC). If a READ
command is registered and the latency is 2 clocks, the first data element will be valid after (t_CK + t_AC). For details please refer
to the READ command description.
Rev.1.0, 2007-03
12
10242006-Y557-TZXW