HYB18M1G16 Datasheet, PDF (11/65 Pages) Qimonda AG – 1-Gbit x16 DDR Mobile-RAM

Data Sheet
2.2
Register Definition
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
2.2.1
Mode Register
The Mode Register is used to define the specific mode of operation of the DDR Mobile-RAM. This definition includes the
selection of a burst length (bits A0-A2), a burst type (bit A3) and a CAS latency (bits A4-A6). The Mode Register is programmed
via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is
programmed again or the device loses power.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any
subsequent operation. Violating either of these requirements results in unspecified operation.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
Mode Register Definition (BA[1:0] = 00_B)
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Field Bits
CL [6:4]
BT 3
BL [2:0]
Type
w
w
w
Description
CAS Latency
010_B CL 2
011_B CL 3
Note: All other bit combinations are RESERVED.
Burst Type
0_B BT Sequential
1_B BT Interleaved
Burst Length
001_B BL 2
010_B BL 4
011_B BL 8
100_B BL 16
Note: All other bit combinations are RESERVED.
2.2.1.1 Burst Length
READ and WRITE accesses to the DDR Mobile-RAM are burst oriented, with the burst length being programmable. The burst
length determines the maximum number of column locations that can be accessed for a given READ or WRITE command.
Burst lengths of 2, 4, 8 or 16 locations are available.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses
for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is
uniquely selected by A1 - A9 when the burst length is set to two, by A₂ - A9 when the burst length is set to four, by A₃ - A9
when the burst length is set to eight and by A₄ - A9 when the burst length is set to sixteen. The remaining (least significant)
address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ
and WRITE bursts.
Rev.1.0, 2007-03
11
10242006-Y557-TZXW