HYB18M1G16 Datasheet, PDF (18/65 Pages) Qimonda AG – 1-Gbit x16 DDR Mobile-RAM

Data Sheet
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
CK
CK
Input
FIGURE 6
Address / Command Inputs Timing Parameters
t_CK
t_CH
t_CL
Valid
t_IS t_IH
Valid
Valid
= Don't Care
Parameter
TABLE 8
Inputs Timing Parameters
Symbol
-6
- 7.5
Unit Note
min. max. min. max.
Clock high-level width
Clock low-level width
Clock cycle time
CL = 3
CL = 2
t_CH
0.45 0.55 0.45 0.55 t_CK
t_CL
0.45 0.55 0.45 0.55 t_CK
t_CK
6
–
7.5
–
ns
12
–
15
–
Address and control input setup time
fast slew rate t_IS
slow slew rate
1.1
–
1.3
–
ns
1.3 –
1.5
–
Address and control input hold time
fast slew rate t_IH
slow slew rate
1.1
–
1.3
–
ns
1.3 –
1.5
–
Address and control input pulse width
t_IPW
2.7
–
3.0
–
ns
1) All AC timing characteristics assume an input slew rate of 1.0 V/ns.
2) The only time that the clock frequency is allowed to change is during power-down, self-refresh or clock stop modes.
3) The transition time for address and command inputs is measured between V_IH and V_IL.
4) For command / address input slew rate ≥ 1V/ns.
5) A CK/CK differential slew rate of 2.0 V/ns is assumed for this parameter.
6) For command / address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns.
7) This parameter guarantees device timing. It is verified by device characterization but are not subject to production test.
1)
1)
1)2)
1)3)4)5)
1)3)6)
1)3)4)
1)3)6)
1)7)
Rev.1.0, 2007-03
18
10242006-Y557-TZXW