CLRC632 Datasheet, PDF (93/163 Pages) NXP Semiconductors – Multiple Protocol Contactless Reader IC

Philips Semiconductors
Multiple Protocol Contactless Reader IC
Product Specification Rev. 3.0; May 2003
CL RC632
10 POWER REDUCTION MODES
10.1 Hard Power Down
A Hard Power Down is enabled with HIGH on pin RSTPD. This turns off all internal current sinks including
the oscillator. All digital input buffers are separated from the input pads and defined internally (except pin
RSTPD itself). The output pins are frozen at a certain value.
This is shown in the following table.
SYMBOL
OSCIN
IRQ
MFIN
MFOUT
TX1
TX2
NWR
NRD
NCS
D0 to D7
ALE
A0
A1
A2
AUX
RX
VMID
RSTPD
OSCOUT
PIN
1
2
3
4
5
7
9
10
11
13 to 20
21
22
23
24
27
29
30
31
32
TYPE
I
O
I
O
O
O
I
I
I
I/O
I
I/O
I
I
O
I
A
I
O
DESCRIPTION
Not separated from input, pulled to AVSS
High impedance
Separated from Input
LOW
HIGH, if TX1RFEn=1
LOW, if TX1RFEn=0
HIGH, only if TX2RFEn=1 and TX2Inv=0
LOW
Separated from Input
Separated from Input
Separated from Input
Separated from Input
Separated from Input
Separated from Input
Separated from Input
Separated from Input
High impedance
Not changed
Pulled to AVDD
Not changed
HIGH
Table 10-1: Signal on Pins during Hard Power Down
10.2 Soft Power Down
The Soft Power Down-mode is entered immediately by setting bit PowerDown in the Control-Register. All
internal current sinks are switched off (including the oscillator buffer).
In difference to the Hard Power Down-mode, the digital input-buffers are not separated by the input pads and
keep their functionality. The digital output pins do not change their state.
After resetting bit PowerDown in the Control-Register it needs 512 clocks until the Soft Power Down mode is
left indicated by the PowerDown bit itself. Resetting it does not immediately clear it. It is cleared
automatically by the CL RC632 when the Soft Power Down-Mode is left.
Note: If the internal oscillator is used, you have to take into account that it is supplied by AVDD and it will
take a certain time t_osc until the oscillator is stable and the clock cycles can be detected by the internal logic.
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