CLRC632 Datasheet, PDF (80/163 Pages) NXP Semiconductors – Multiple Protocol Contactless Reader IC

Philips Semiconductors
Multiple Protocol Contactless Reader IC
Product Specification Rev. 3.0; May 2003
CL RC632
7 FIFO BUFFER
7.1 Overview
An 8x64 bit FIFO buffer is implemented in the CL RC632 acting as a parallel-to-parallel converter. It buffers
the input and output data stream between the µ-Processor and the internals of the CL RC632. Thus, it is
possible to handle data streams with lengths of up to 64 bytes without taking timing constraints into account.
7.2 Accessing the FIFO Buffer
7.2.1 ACCESS RULES
The FIFO-buffer input and output data bus is connected to the FIFOData Register. Writing to this register
stores one byte in the FIFO-buffer and increments the internal FIFO-buffer write-pointer. Reading from this
register shows the FIFO-buffer contents stored at the FIFO-buffer read-pointer and increments the FIFO-
buffer read-pointer. The distance between the write- and read-pointer can be obtained by reading the
FIFOLength Register.
When the µ-Processor starts a command, the CL RC632 may, while the command is in progress, access the
FIFO-buffer according to that command. Physically only one FIFO-buffer is implemented, which can be used
in input- and output direction. Therefore the µ-Processor has to take care, not to access the FIFO-buffer in
an unintended way.
The following table gives an overview on FIFO access during command processing:
Active Command
StartUp
Idle
Transmit
Receive
Transceive
WriteE2
ReadE2
LoadKeyE2
LoadKey
Authent1
Authent2
LoadConfig
CalcCRC
µ-Processor is allowed to
Write to FIFO Read from FIFO
Remark
-
-
-
-
-
-
µ-Processor has to know the actual state of the command
(transmitting or receiving)
-
The µ-Processor has to prepare the arguments,
afterwards only reading is allowed
-
-
-
-
-
-
-
Table 7-1: Allowed Access to the FIFO-Buffer
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