CLRC632 Datasheet, PDF (131/163 Pages) NXP Semiconductors – Multiple Protocol Contactless Reader IC

Philips Semiconductors
Multiple Protocol Contactless Reader IC
Product Specification Rev. 3.0; May 2003
CL RC632
18.6.1.3 Timing Diagram
The following diagram shows programming of 5 bytes into the E²PROM:
NWrite
t_prg,del
Data
Write Adr
E2 LSB
Adr
MSB
Byte0
WriteE2
command active
E²PROM
Programming
Byte1
E2Ready
Byte2
Byte3
t_prog
Programming Byte0
Byte4
t_prog
Programming Byte1, Byte2, and Byte3
t_prog
Programming Byte4
Idle
Cmd
TxIRq
Figure 18-7: Timing Diagram for E²PROM programming
Explanation: It is assumed, that the CL RC632 finds and reads Byte 0 before the µ-Processor is able to write
Byte 1 (t_prog,del = 300 ns). This causes the CL RC632 to start the programming cycle, which needs about
t_prog = 5.8 ms. In the meantime the µ-Processor stores Byte 1 to Byte 4 to the FIFO buffer. Assuming, that the
E²PROM starting byte-address is e.g. 16C_hex then Byte 0 is stored exactly there. The CL RC632 copies the
following data bytes into the E²PROM input buffer. Copying Byte 3, it detects, that this data byte has to be
programmed at the E²PROM byte-address 16F_hex. Since this is the end of the memory block, the CL RC632
automatically starts a programming cycle. In the next turn, Byte 4 will be programmed at the E²PROM byte-
address 170_hex. Since this is the last data byte, the flags (E2Ready and TxIRq) that indicate the end of the
E²PROM programming activity will be set.
Although all data has been programmed into the E2PROM, the CL RC632 stays in the WriteE2-Command.
Writing further data to the FIFO would lead to further E²PROM programming, continuing at the E²PROM
byte-address 171_hex. The command is stopped using the Idle-Command.
18.6.1.4 Error Flags for the WriteE2 Command
Programming is inhibited for the E²PROM blocks 0 (E²PROM’s byte-address 00_hex to 0F_hex). Programming to
these addresses sets the flag AccessErr. No programming cycle is started. Addresses above 1FF_hex are
taken modulo 200_hex (for the E²PROM memory organisation, refer to chapter 6.).
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