CLRC632 Datasheet, PDF (154/163 Pages) NXP Semiconductors – Multiple Protocol Contactless Reader IC

Philips Semiconductors
Multiple Protocol Contactless Reader IC
Product Specification Rev. 3.0; May 2003
CL RC632
22.5.2.2 Bus Timing for Common Read/Write Strobe
SYMBOL
t_LHLL
t_AVLL
t_LLAX
t_LLSL
t_CLSL
t_SHCH
t_SLDV,R
t_SHDZ
t_SLDV,W
t_SHDX
t_SHRX
t_SLSH
t_AVSL
t_SHAX
t_SHSL
t_RVSL
PARAMETER
MIN
AS pulse width
20
Multiplexed Address Bus valid to AS low (Address Set Up Time)
15
Multiplexed Address Bus valid after AS low (Address Hold Time)
8
AS low to NDS low
15
NCS low to NDS low
0
NDS high to NCS high
0
NDS low to DATA valid (for read cycle)
NDS low to DATA high impedance (read cycle)
NDS low to DATA valid (for write cycle)
DATA hold after NDS high (write cycle, Hold Time)
8
R/NW hold after NDS high
8
NDS pulse width
65
Separated Address Bus valid to NDS low (Hold Time)
30
Separated Address Bus valid after NDS high (Set Up Time)
8
period between sequenced read/write accesses
150
R/NW valid to NDS low
8
MAX
65
20
35
Table 22-11: Timing Specification for Common Read/Write Strobe
t_LHLL
ALE
NCS
t_CLSL
t_SHCH
R/NW
t_RVSL
t_SHRX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NDS
t_SHSL
t_LLSL
t_SLSH
t_SHSL
D0 ... D7
A0 ... A2
t_AVLL
t_LLAX
Multiplexed Addressbus
A0 ... A2
t_SLDV,R
t_SLDV,W
D0 ... D7
t_SHDX
t_SHDZ
t_AVSL
Separated Addressbus
A0 ... A2
t_SHAX
Figure 22-2: Timing Diagram for Common Read/Write Strobe
Note: For separated address and data bus the signal ALE is not relevant and the multiplexed addresses on the data bus don’t
care. For the multiplexed address and data bus the address lines A0 to A2 have to be connected as described in 4.3.
154
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