CLRC632 Datasheet, PDF (155/163 Pages) NXP Semiconductors – Multiple Protocol Contactless Reader IC

Philips Semiconductors
Multiple Protocol Contactless Reader IC
Product Specification Rev. 3.0; May 2003
CL RC632
22.5.2.3 Bus Timing for EPP
SYMBOL
t_LLLH
t_AVLH
t_LHAX
t_CLSL
t_SHCH
t_SLDV,R
t_SHDZ
t_SLDV,W
t_SHDX
t_SHRX
t_SLSH
t_RVSL
t_SLWH
t_SHWL
PARAMETER
MIN
MAX
nAStrb pulse width
20
Multiplexed Address Bus valid to nAStrb high (Set Up Time)
15
Multiplexed Address Bus valid after nAStrb high (Hold Time)
8
NCS low to nDStrb low
0
nDStrb high to NCS high
0
nDStrb low to DATA valid (read cycle)
65
nDStrb low to DATA high impedance (read cycle)
20
nDStrb low to DATA valid (write cycle, Set up Time)
35
DATA hold after nDStrb high (write cycle, Hold Time)
8
nWrite hold after nDStrb high
8
nDStrb pulse width
65
nWrite valid to nDStrb low
8
nDStrb low to nWait high
75
nDStrb high to nWait low
75
Table 22-12: Timing Specification for Common Read/Write Strobe
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NCS
nWrite
t_CLSL
t_RVSL
t_SHCH
t_SHRX
nDStrb
nAStrb
D0 ... D7
t_SLSH
t_SLDV,R
t_SLDV,W
D0 ... D7
A0 ... A7
t_SHDX
t_SHDZ
nWait
t_SLWH
t_SHWL
Figure 22-3: Timing Diagram for Common Read/Write Strobe
Remark: The figure does not distinguish between the Address Write Cycle and a Data Write Cycle. Take in
account, that timings for the Address Write and Data Write Cycle are different. For the EPP-Mode the
address lines A0 to A2 have to be connected as described in 4.3.
155
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