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XA-C3 Datasheet, PDF (8/68 Pages) NXP Semiconductors – XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce | |||
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Philips Semiconductors
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
Preliminary specification
XA-C3
GENERAL DESCRIPTION
The XAâC3 is a member of the Philips XA (eXtended Architecture)
family of highâperformance 16âbit singleâchip microcontrollers. The
XAâC3 combines an array of standard peripherals together with a
PeliCAN CAN 2.0B engine and unique âMessage Managementâ
hardware to provide integrated support for most CAN Transport
Layer (CTL) protocols such as DeviceNet, CANopen and OSEK. For
additional details, refer to the XA-C3 Overview on page 35.
The XA architecture supports:
D Easy 16-bit migration from the 80C51 architecture.
D 16âbit fully static CPU with 24âbit addressed PROGRAM and
DATA spaces.
D Twentyâone 16âbit CPU core registers capable of all arithmetic
and logic operations while serving as memory pointers.
D An enhanced orthogonal instruction set tailored for highâlevel
support of the C language.
D Multiâtasking and direct realâtime executive support.
D Lowâpower operation intrinsic to the XA architecture includes
PowerâDown and Idle modes.
FEATURES IN COMMON WITH XA-G3
D Pinâcompatibility (CAN RxD and CAN TxD use the XA-G3 NC
pins).
D 32K bytes of onâchip EPROM PROGRAM memory (see Table 1).
D 44âpin PLCC (Figure 1 and Table 2) and 44âpin LQFP (Figure 2
and Table 3) packages.
D Commercial (0 to 70oC) and Industrial (â40 to 85oC) ranges.
D Supports offâchip addressing of PROGRAM and DATA memory
up to 1 megabyte each (20 address lines).
D Three standard counter/timers (T0, T1, and T2) with
enhancements such as Auto Reload for PWM outputs.
D UARTâ0 with enhancements such as separate Rx and Tx
interrupts, Break Detection, and Automatic Address Recognition.
D Watchdog with a secure WFEED1 / WFEED2 sequence.
D Four 8âbit I/O ports with 4 programmable output configurations
per pin.
XA-C3 SPECIFIC FEATURES
D 32 MHz operating frequency at 4.5 to 5.5V operation.
D One Serial Port Interface (SPI)
D 1024 bytes of onâchip DATA RAM.
D 42 vectored interrupts. These include 13 maskable Events, 7
Software interrupts, 6 Exceptions, 16 software Traps, segmented
DATA memory, multiple User stacks, and banked registers to
support rapid context switching.
D External interfacing via a 16âbit DATA bus width.
XA-C3 CAN AND CTL FEATURES
D A PeliCAN CAN 2.0B engine from the SJA1000 Standâalone CAN
controller which supports 11â and 29âbit IDentifiers and the
maximum CAN data rate (1 Mbps) and CAN Diagnostics.
D Hardware âMessage Managementâ support for all major CTL
protocols: DeviceNet, CANopen, OSEK.
D Automatic (hardware) assembly of Fragmented Messages via a
Transport Layer Co-Processor. Concurrent assembly of up to 32
separate interleaved Fragmented Messages
D 32 CAN Transport Layer (CTL) Message Objects are modelled as
a FullCAN Object Superset.
D 32 separate filters/screeners (one per Message Object), each
allowing a 30âbit ID Match and full 29âbit Mask (i.e., each
filter/screener represents a unique Group address).
D Each Message Object can be configured as Receive or Transmit.
D A separate message buffer is associated with each CTL Message
Object. 32 message buffers are located in XRAM and managed
by 32 DMA channels. Message buffer size for each Message
Object is independently configurable in length (from 2 to 256
bytes).
D For singleâchip systems there is a 512âbyte (onâchip) XRAM
message buffer, independent of the 1K onâchip DATA RAM, which
is extendable (offâchip) to 8K bytes (i.e., 32 Message Objects that
can be up to 256 bytes each).
LOGIC SYMBOL AND BLOCK DIAGRAM
Refer to Figure 3 for the logic symbol for the XA-C3 and to Figure 4
for a simplified block diagram representation.
UPGRADING XA-G3 DESIGNS TO CAN
D XA-G3 NC pins are XA-C3 CAN RxD and CAN TxD pins.
D XA-G3 UARTâ1 is replaced by a Serial Port Interface (SPI)
D XA-C3 software must never write to the BCR register
D XA-C3 software must initialize BTRH and BTRL with 00h
2000 Jan 25
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