XA-C3 Datasheet, PDF (31/68 Pages) NXP Semiconductors – XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce

Philips Semiconductors
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
Preliminary specification
XA-C3
RST/Pin Properties and Requirements
D Active LOW for improved noise immunity
D Schmitt Trigger with Threshold = 0.7 Vdd
D RST/ must be low for the longer of 10 µs or 10 clocks
D If EA/ = 1, all Port pins are set to Quasi–Bidirectional mode
D If EA/ = 0, all External Bus pins are set to Push–Pull mode
Power-On Reset
D Must be > 10 msec to allow the on–chip oscillator to stabilize
Other Reset Effects
D Register File is zeroed except [R7] USP/SSP is set to 100h
D Internal DATA RAM is not affected
D All maskable interrupts are disabled
D DS, ES, CS, SSEL, PZ, CM, PT0 and PT1 are zeroed
D The Watchdog Timer is turned ON
Reset Timing
The EA/ pin is sampled on the rising edge of the Reset (RST/) pulse.
The result of this sampling determines whether the device is to
begin execution from internal or External PROGRAM memory.
Specifically, if EA/ is pulled high, the XA starts in Single–Chip mode.
Lastly, after RST/ is released, the {WAIT ; V_pp ; EA/} pin becomes a
bus WAIT signal for External bus transactions.
P3.5 is weakly pulled high whenever RST/ is asserted. Given EA/
is used at RESET to request code starts from External memory, this
weak pull up assures the PXAC3 will set–up a 16 bit External bus.
Thus, if External code operation is desired, the User must NEVER
put a LOW on P3.5 during RESET.
Note: EA/ must be held for eight equivalent oscillator clock periods
after RST/ is deasserted (i.e., after RST/ returns to ONE) to
guarantee that the desired EA/ value is latched correctly.
The relationship of EA/ timing with respect to both RST/ and ALE
signals is shown in Figure 20.
RST/
< 1 CLK
At least 8 equivalent CLK periods
EA/
EA/ Held Stable
ALE
Alternate “Hold” reference
At least 5 equivalent CLK periods
Figure 20. EA/ Timing Diagram
SU01333
Power Reduction Modes
The XA–C3 supports Idle and Power–Down modes of power
reduction. The Idle mode leaves some peripherals running to allow
them to wake up the processor when an interrupt is generated. The
Power–Down mode stops the oscillator in order to minimize power.
The processor can be made to exit Power–Down mode via Reset or
one of the External interrupt inputs. In order to use an External
interrupt to re–activate the XA while in Power–Down mode, the
External interrupt must be enabled and be configured to
level–sensitive mode. In Power–Down mode, the power supply
voltage may be reduced to the RAM keep–alive voltage (2V),
retaining the RAM, register, and SFR values at the point where the
Power–Down mode was entered.
Interrupts
Interrupt Types
There are four types of interrupts:
D Event Interrupts – service peripherals such as UARTs and
timers.
D Software Interrupts – demote the priority level of a running Event
Interrupt below the lowest Event priority level (i.e., 9), thereby
permitting lower priority Event Interrupts to run.
D Trap Interrupts –accomplish multi–tasking services, such as
RTOS, via non–maskable interrupts.
2000 Jan 25
24