XA-C3 Datasheet, PDF (62/68 Pages) NXP Semiconductors – XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce

Philips Semiconductors
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
Offset FFFh
MMR Space
Preliminary specification
XA-C3
Offset 1FFh
512 Bytes Object Registers
Offset 000h
SU01341
Figure 44. Detail of MMR space showing block of Message Object Registers
Special Function Register MRBH
D Address: SFR 497h
D Reset Value: 0Fh
MRBH
7
6
5
4
3
2
1
0
a23 – a16 of MMR Base Address
Special Function Register MRBL
D Address: SFR 496h
MRBL
7
6
5
4
a15 – a12 of MMR Base Address
D Reset Value: F0h
3
2
–
–
1
0
–
MRBE
MRBE
MRBE is the global enable bit for MMRs. On
reset, MRBE is cleared to 0.
0 = MMRs disabled
1 = MMRs enabled
On–Chip Message Buffer RAM (XRAM)
The XA-C3 has a 512–byte on–chip message buffer RAM (XRAM)
which may contain part or all of the CAN/CTL (transmit & receive
objects) message buffers. This block of memory can be accessed
as regular data memory. The logic address of the XRAM is
programmed by software, and must start at a 512–Byte boundary.
The base address of the XRAM is determined by the contents of
Memory Mapped Registers MBXSR and XRAMB as shown in and .
Any address asserted by the XA core (or the DMA) whose fifteen
most significant bits match the concatenation
MBXSR[7:0]XRAMB[7:1] will be automatically routed to the XRAM.
On reset, the XRAM is disabled. Note: The XRAM should not be
confused with the 1K Byte “scratch–pad” DATA RAM which is also
provided on–chip.
Since the uppermost 8 bits of all message buffer addresses are
formed by the contents of the MBXSR register, the XRAM and all 32
message buffers must reside in the same 64K byte data memory
segment. Since the XA-C3 only provides address lines A1 – A19 for
accessing External memory, all External memory addresses must
be within the lowest 1M byte of address space. Therefore, if there is
External memory in the system into which any of the 32 message
buffers will be mapped, then all 32 message buffers and the XRAM
must also be mapped entirely into that same 64K byte segment,
which must be below the 1M byte address limit.
2000 Jan 25
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