XA-C3 Datasheet, PDF (57/68 Pages) NXP Semiconductors – XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce

Philips Semiconductors
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
Preliminary specification
XA-C3
If the Receive Pre–Buffer overflows, the PBO status flag in
FESTR[5] will be set, generating a Frame Error interrupt, if enabled.
The PBO status flag is cleared by writing ‘1’ to the flag’s bit position.
Since this error will be generated before any acceptance filtering has
been performed, there will be no Message Object number
associated with the error (hence its inclusion under the category of
frame error). Note that the new message being ignored may be
intended for some other device on the CAN bus. This error should
never occur unless there is a serious system–design problem (e.g.,
an off–chip device grabs the bus and fails to de–assert “WAIT” for
an extended period).
Arbitration Lost
During transmission, arbitration on the CAN bus can be lost to a
competing device with a higher priority CAN Identifier. In this case,
the ARBLST status flag in FESTR[4] will be set, generating a Frame
Error interrupt if enabled. The ARBLST status flag is cleared by
executing a read of the Arbitration Lost Capture Register.
The bit position in the CAN Identifier at which arbitration was lost will
be encoded and stored in the Arbitration Lost Capture Register
(ALCR) for the benefit of the User application. The ALCR must be
read by the CPU in order to be reactivated for capturing the next
arbitration lost code, as well as to clear the ARBLST status flag. The
bit position in the CAN ID is encoded and stored in the 5–bit field
ALCR[4:0]. ALCR[7:5] are reserved, and are always read as zeros.
The 5–bit number latched into ALCR is interpreted according to
Table 26.
Table 26. Arbitration Lost Codes
ALCR[4:0]
Interpretation
0
Arbitration lost in ID28
1
Arbitration lost in ID27
2
Arbitration lost in ID26
...
...
10
Arbitration lost in ID18
11
Arbitration lost in SRR bit
12
Arbitration lost in IDE bit
13
Arbitration lost in ID17 (Extended Frame only)
...
...
30
Arbitration lost in ID0 (Extended Frame only)
31
Arbitration lost in RTR bit (Extended Frame only)
Error Warning
The EW bit in CANSTR[5] reports the error status of the core, with
regard to the Error Warning Limit defined by the User. If EW is ‘0’,
then both the Tx and Rx Error Counters contain values less than
that stored in the Error Warning Limit Register. If either counter
reaches or exceeds the value stored in the EWLR register, then the
EW bit will be set to ‘1’. Subsequently if both counters decrement
below the value stored in the EWLR register, the EW bit will be
cleared to ‘0’.
The ERRW status flag in FESTR[1] will be set each time the EW bit
in CANSTR[5] changes state, generating a Frame Error interrupt, if
enabled. That is, both the 0–to–1 and the 1–to–0 transitions of the
EW bit will cause the ERRW status flag to be set. The ERRW status
flag is cleared by writing ‘1’ to the flag’s bit position.
Error Passive
The EP bit in CANSTR[6] reflects the Error Passive status of the
core. If either the Tx or Rx Error Counter equals or exceeds the
predefined value 128d, the EP bit will be set to ‘1’. Subsequently, if
both counters decrement below 128d, the EP bit will be cleared to
‘0’.
Both 0–to–1 and 1–to–0 transitions of the EP bit will cause the
ERRP status flag to be set, generating a Frame Error interrupt if
enabled. The ERRP status flag is cleared by writing ‘1’ to the flag’s
bit position in FESTR[0].
Bus Off
The BS (Bus Status) bit in CANSTR[7] reflects the Bus–On and
Bus–Off status of the core. BS = 0 means the CAN core is currently
involved in bus activity (Bus–On), while BS = 1 means it is not
(Bus–Off).
When the Transmit Error Counter exceeds the predefined value
255d, the BS bit is set to ‘1’ (Bus–Off). In addition, the RR bit is set
to ‘1’ (putting the CAN Core into Reset mode), and the BOFF status
flag is set, generating a Frame Error interrupt if enabled. The
Transmit Error Counter is preset to 127d, and the Receive Error
Counter is cleared to 00h. The CAN Core will remain in this state
until it is returned to Normal mode by clearing the RR bit.
Once the RR bit is cleared, the Tx Error Counter will decrement
once for each occurrence of the Bus–Free signal (11 consecutive
recessive bits). After 128 occurrences of Bus–Free, the BS bit is
cleared (Bus–On). Again, the BOFF status flag is set (generating
another Frame Error interrupt if enabled). At this point, both the Tx
and Rx Error counters will contain the value 00h. At any time during
the Bus–Off condition (BS = 1), the CPU can determine the progress
of the Bus–Off recovery by reading the contents of the Tx Error
Counter.
During Bus–Off, a return to Bus–On can be expedited under
software control. If BS = 1, writing a value between 0 and 254 to the
Tx Error Counter and then clearing the RR bit will cause the BS bit
to be cleared after only 1 occurrence of the Bus–Free signal. As in
the case above, on the 1–to–0 transition of the BS bit, the BOFF
status flag will be set, generating another Frame Error interrupt if
enabled.
The CPU can also initiate a Bus–Off condition, if the CAN Core is
first put into Reset mode by setting RR = 1. Next, the value 255 is
written to the Tx Error Counter, and the RR bit is cleared. With the
core back in Normal mode, the Tx Error Counter contents are
interpreted, and the Bus–Off condition proceeds as described
above, exactly as if it had been caused by bus errors.
Note that the Tx Error Counter can only be written to when the CAN
Core is in Reset mode, and that both 0–to–1 and 1–to–0 transitions
of the BS bit will cause the BOFF status flag to be set, generating
Frame Error interrupts if enabled.
CAN Interrupt Registers
CANINTFLG (CAN Interrupt Flag Register)
D Address: MMR base + 228h
D Access: Read/Clear, byte or word
D Reset Value: 00h
CANINTFLG
765
4
– – – FERIF
3
MERIF
2
RBFIF
1
TMCIF
0
RMCIF
FERIF
Frame Error Interrupt Flag (this bit is
Read–Only, and must be cleared in FESTR)
2000 Jan 25
50