XA-C3 Datasheet, PDF (35/68 Pages) NXP Semiconductors – XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce

Philips Semiconductors
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
Preliminary specification
XA-C3
AC ELECTRICAL CHARACTERISTICS
Table 20. AC Electrical Characteristics
V_DD = 4.5V to 5.5V; T_amb = 0 to +70°C for commercial, –40°C to +85°C for industrial.
SYMBOL Figure
PARAMETER
External Clock
f_C
t_C
22
t_CHCX
22
t_CLCX
22
t_CLCH
22
t_CHCL
22
Address Cycle
t_CRAR
21
t_LHLL
16
t_AVLL
16
t_LLAX
16
Code Read Cycle
t_PLPH
16
t_LLPL
16
t_AVIVA
16
t_AVIVB
17
t_PLIV
16
t_PXIX
16
t_PXIZ
16
t_IXUA
16
Data Read Cycle
t_RLRH
18
t_LLRL
18
t_AVDVA
18
t_AVDVB
19
t_RLDV
18
t_RHDX
18
t_RHDZ
18
t_DXUA
18
Data Write Cycle
t_WLWH
20
t_LLWL
20
t_QVWX
20
t_WHQX
20
t_AVWL
20
t_UAWH
20
WAIT Input
t_WTH
21
t_WTL
21
Oscillator frequency
Clock period and CPU timing cycle
Clock high time
Clock low time
Clock rise time
Clock fall time
Delay from clock rising edge to ALE rising edge
ALE pulse width (programmable)
Address valid to ALE de–asserted (set–up)
Address hold after ALE de–asserted
PSEN/ pulse width
ALE de–asserted to PSEN/ asserted
Address valid to instruction valid, ALE cycle (access time)
Address valid to instruction valid, non–ALE cycle (access time)
PSEN/ asserted to instruction valid (enable time)
Instruction hold after PSEN/ de–asserted
Bus 3–State after PSEN/ de–asserted (disable time)
Hold time of unlatched part of address after instruction latched
RD/ pulse width
ALE de–asserted to RD/ asserted
Address valid to data input valid, ALE cycle (access time)
Address valid to data input valid, non–ALE cycle (access time)
RD/ low to valid data in, enable time
Data hold time after RD/ de–asserted
Bus 3–State after RD/ de–asserted (disable time)
Hold time of unlatched part of address after data latched
WR/ pulse width
ALE falling edge to WR/ asserted
Data valid before WR/ asserted (data setup time)
Data hold time after WR/ de–asserted (Note 6)
Address valid to WR/ asserted (address setup time) (Note 5)
Hold time of unlatched part of address after WR/ is de–asserted
WAIT stable after bus strobe (RD/, WR/, or PSEN/) asserted
WAIT hold after bus strobe (RD/, WR/, or PSEN/) assertion
VARIABLE CLOCK
MIN
MAX
UNIT
0
32
1/f_C
t_C * 0.5
t_C * 0.4
5
5
MHz
ns
ns
ns
ns
ns
10
46
ns
(V1 * t_C) – 6
ns
(V1 * t_C) – 12
ns
(t_C/2) – 10
ns
(V2 * t_C) – 10
ns
(t_C/2) – 7
ns
(V3 * t_C) – 36
ns
(V4 * t_C) – 29
ns
(V2 * t_C) – 29
ns
0
ns
t_C – 8
ns
0
ns
(V7 * t_C) – 10
ns
(t_C/2) – 7
ns
(V6 * t_C) – 36
ns
(V5 * t_C) – 29
ns
(V7 * t_C) – 29
ns
0
ns
t_C – 8
ns
0
ns
(V8 * t_C) – 10
ns
(V12 * t_C) – 10
ns
(V13 * t_C) – 22
ns
(V11 * t_C) – 5
ns
(V9 * t_C) – 22
ns
(V11 * t_C) – 7
ns
(V10 * t_C) – 5
(V10 * t_C) – 30 ns
ns
NOTES:
1. Load capacitance for all outputs = 80pF.
2. Variables V1 through V13 reflect programmable bus timing, which is
programmed via the Bus Timing registers (BTRH and BTRL).
Refer to the XA User Guide for details of the bus timing settings.
V1) This variable represents the programmed width of the ALE pulse
as determined by the ALEW bit in the BTRL register.
V1 = 0.5 if the ALEW bit = 0, and 1.5 if the ALEW bit = 1.
V2) This variable represents the programmed width of the PSEN/ pulse
as determined by the CR1 and CR0 bits or the CRA1, CRA0, and
ALEW bits in the BTRL register.
– For a bus cycle with no ALE, V2 = 1 if CR1/0 = 00, 2 if CR1/0
= 01, 3 if CR1/0 = 10, and 4 if CR1/0 = 11. Note that during
burst mode code fetches, PSEN/ does not exhibit transitions at
the boundaries of bus cycles. V2 still applies for the purpose of
determining peripheral timing requirements.
– For a bus cycle with an ALE, V2 = the total bus cycle duration
(2 if CRA1/0 = 00, 3 if CRA1/0 = 01, 4 if CRA1/0 = 10,
and 5 if CRA1/0 = 11) minus the number of clocks used by
ALE (V1 + 0.5).
Example: If CRA1/0 = 10 and ALEW = 1, the V2 = 4 – (1.5 +
0.5) = 2.
V3) This variable represents the programmed length of an entire code
read cycle with ALE. This time is determined by the CRA1 and
CRA0 bits in the BTRL register. V3 = the total bus cycle duration (2
if CRA1/0 = 00, 3 if CRA1/0 = 01, 4 if CRA1/0 = 10,
and 5 if CRA1/0 = 11).
2000 Jan 25
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