XA-C3 Datasheet, PDF (59/68 Pages) NXP Semiconductors – XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce

Philips Semiconductors
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
Preliminary specification
XA-C3
MCPLH
15
14
Obj31 Obj30
13
Obj29
12
Obj28
11
Obj27
10
Obj26
9
Obj25
8
Obj24
7
Obj23
6
Obj22
5
Obj21
4
Obj20
3
Obj19
2
Obj18
1
Obj17
0
Obj16
MCPLL (Message Complete Status Flags Low)
D Address: MMR base + 224h
MCPLL
15
14
Obj15 Obj14
13
Obj13
12
Obj12
11
Obj11
10
Obj10
9
Obj9
D Access: Read/Clear, byte or word
D Reset Value: 0000h
8
7
6
5
4
3
Obj8 Obj7 Obj6 Obj5 Obj4 Obj3
2
Obj2
1
Obj1
0
Obj0
TxERC (Tx Error Counter)
D Address: MMR base + 274h
TXERC
7
6
5
4
TC₇
TC₆
TC₅
TC₄
The Tx Error Counter can only be written to when the CAN Core is
in Reset mode. Hardware will preset the register to 128 when a
Bus–Off condition occurs. See the section entitled Bus Off on page
50 for details.
RXERC
7
6
5
4
RC₇
RC₆
RC₅
RC₄
The Rx Error Counter can only be written to when the CAN Core is
in Reset mode. When a Bus–Off condition occurs, this register is
cleared to 00h.
EWLR (Error Warning Limit Register)
D Address: MMR base + 276h
EWLR
7
EWL₇
6
EWL₆
5
EWL₅
4
EWL₄
ECCR (Error Code Capture Register)
D Address: MMR base + 278h
ECCR
7
6
5
4
EC1
EC0
D Access: Read, write, R/M/W, byte or word
D Reset Value: 00h
3
2
1
TC₃
TC₂
TC₁
RxERC (Rx Error Counter)
D Address: MMR base + 275h
D Access: Read, write, R/M/W, byte or word
D Reset Value: 00h
3
RC₃
2
RC₂
1
RC₁
D Access: Read, write, R/M/W, byte or word
D Reset Value: 96h
3
EWL₃
2
EWL₂
1
EWL₁
D Access: Read, write, R/M/W, byte or word
D Reset Value: 00h
3
2
1
State
0
TC₀
0
RC₀
0
EWL₀
0
The Error Code Capture Register contains detailed information
about the most recent Bus Error. See Table 25 for details. The
register must be read in order to be re–enabled for capturing the
next error code, as well as to clear the BERR status flag. This
register should be read before enabling the Bus Error interrupt.
ALCR (Arbitration Lost Capture Register)
D Address: MMR base + 27Ah
D Access: Read, write, R/M/W, byte or word
D Reset Value: 00h
ALCR
7
6
5
4
3
2
1
0
–
–
–
Bit Number
The ALCR latches the bit number in the CAN Identifier where the
most recent Arbitration Lost occurred. See Table 26 for details. The
register must be read in order to be reenabled for capturing the next
arbitration lost code, as well as to clear the ARBLST status flag.
This register should be read before enabling the Arbitration Lost
interrupt.
2000 Jan 25
52