XA-C3 Datasheet, PDF (45/68 Pages) NXP Semiconductors – XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce

Philips Semiconductors
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
Preliminary specification
XA-C3
Location of Sample Point
The location of the sample point within a bit period is determined
according to the following:
one bit period
tSYNC–
SEG
tSEG1
tSEG2
Sample point
SU01339
D tSYNCSEG = tSCL
D tSEG1 = tSCL ∗ (8 ∗ tSEG1.3 + 4 ∗ tSEG1.2 + 2 ∗ tSEG1.1 +
tSEG1.0 + 1)
CANBTR
15
14
SAM
TSEG2.2
13
TSEG2.1
12
TSEG2.0
11
TSEG1.3
10
TSEG1.2
9
TSEG1.1
8
TSEG1.0
D tSEG2 = tSCL ∗ (4 ∗ tSEG2.2 + 2 ∗ tSEG2.1 + tSEG2.0 + 1)
where tSEG1.3 – tSEG1.0 and tSEG2.2 – tSEG2.0 are bits in
CANBTR.
Synchronization Jump Width
To compensate for phase shifts between clock oscillators of different
bus controllers, any bus controller must re–synchronize on any
relevant signal edge of the current transmission. The
Synchronization Jump Width defines the maximum number of CAN
System Clock cycles that a bit period may be shortened or
lengthened by one re–synchronization, and is given by the following
expression:
D tSJW = tSCL ∗ (2 ∗ SJW.1 + SJW.0 + 1)
where SJW.1 and SJW.0 are bits in CANBTR.
CANBTR: CAN Bus Timing Register
D Address: MMR base + 272h
D Access: Read, Write during reset mode only. Word access only.
D Reset value: 0000h
7
SJW.1
6
SJW.0
5
BRP.5
4
BRP.4
3
BRP.3
2
BRP.2
1
BRP.1
0
BRP.0
CAN Command and Status Registers
Two Modes in CAN Core Operation
The CCB has two different modes of operation: Reset mode, and
Operation mode. On hardware reset, the CAN core is in Reset
mode, and the RR bit of CANCMR (CAN Command Register) will
be set. The User application would usually set up registers, etc.,
then put the CCB into Operation mode by clearing the RR bit.
While in Operation mode, the following conditions will cause the RR
bit to be set, putting the CCB back into Reset mode:
D Tx Buffer Underflow (TBUF)
CANCMR
7
6
RXP
ST
5
4
LO
Reserved
D Bus Off
D Hardware reset
D Test mode (Refer to XA-C3 User Guide, Sections 2.2.2.1 and
2.7.1.2)
CANCMR: CAN Command Register
D Address: MMR base + 270h
D Access: Read/Write, no R/M/W, Byte or Word Access. Hardware
can set bit 0.
D Reset value: 01h
3
2
1
0
SLPEN
OC1
Reserved
RR
RXP
ST
LO
Reserved
SLPEN
OC1
CANSTR
7
BS
Rx Polarity, writable during reset mode only.
0 = non–inverted, 1 = inverted.
Self test, disable TxACK
Listen only
Reserved bit.
CTL will go back to idle if no interrupt is
generated.
Output control for Tx pad. 0 = Push–Pull,
1 = Open Drain
6
5
4
EP
EW
TS
Reserved
RR
Reserved bit
Reset Request.
CANSTR: CAN Status Register
D Address: MMR base + 271h
D Access: Read only, no write, no R/M/W. Byte access OK.
Hardware can set or clear bits 7 – 2.
D Reset value: 00h
3
2
1
0
RS
SLPOK
–
–
BS
Bus status
EP
Error passive
EW
Error warning
TS
Transmit status
RS
SLPOK
Receive status
CAN status: no CAN bus activity and no
pending core interrupts
2000 Jan 25
38