XA-C3 Datasheet, PDF (44/68 Pages) NXP Semiconductors – XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce

Philips Semiconductors
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
Preliminary specification
XA-C3
objects having the same ID. An alternate option bases transmit
pre–arbitration exclusively on transmit object number, i.e.,
independent of arbitration ID.
Remote Frame Handling
The XA-C3 supports Remote CAN Frames.
memory can be extended off–chip, if desired, starting at address
008000h. The code memory address space extends to 0FFFFFh.
0FFFFFh
Code Memory
MEMORY MAPS
Data Memory Space
1K byte of internal data memory (Scratch Pad) populates the very
bottom of data memory space, in Segment 0 by definition. The
Memory Mapped Registers and the on–chip XRAM can also be
mapped into Segment 0 (as shown in Figure 36), or into any other
segment.
Data Memory Segment 0
00FFFFh
Off–Chip
Off–Chip
4K Bytes
MMR Space
Off–Chip
MMR Base Address
512 Bytes
XRAM
XRAM Base Address
Off–Chip
0003FFh
On–Chip Data Memory
(Scratch Pad)
000000h
SU01337
Figure 36. MMRs and XRAM mapped into Segment 00h.
Code Memory Space
32K Bytes of Internal Code Memory populate addresses 000000h –
007FFFh of code memory space. As shown in Figure 37, code
007FFFh
Internal Code Memory
008000h
000000h
SU01338
Figure 37. External Code Memory starts at 008000h.
CAN CORE BLOCK (CCB)
CAN Bus Timing
CAN System Clock
The CCB has a programmable internal system clock, whose period
is denoted by tSCL. The CAN System Clock is derived from the XA
Oscillator Clock based on the following expression:
D tSCL =2 ∗ tCLK ∗ (32 ∗ BRP.5 + 16 ∗ BRP.4 + 8 ∗ BRP.3 + 4 ∗
BRP.2 + 2 ∗ BRP.1 + BRP.0 + 1)
where tCLK is the period of the XA Oscillator Clock, and BRP.5 –
BRP.0 are bits in the MMR CAN Bus Timing Register (CANBTR).
The length of a bit period in a CAN Frame is expressed in terms of
number of CAN System Clocks.
Samples Per Bit
The number of samples per bit is determined by the value of the
SAM bit in CANBTR.
D SAM = 0 The bus is sampled once per bit (as shown below)
D SAM = 1 The bus is sampled three times per bit (as shown
below)
2000 Jan 25
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