XA-C3 Datasheet, PDF (47/68 Pages) NXP Semiconductors – XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce

Philips Semiconductors
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
Preliminary specification
XA-C3
OBJECT N MATCH ID FIELD (MNMIDH AND MNMIDL)
Mid28 – Mid18
Mid17 – Mid10
Mid9 – Mid2
Mid1 Mid0 MIDE
OBJECT N MASK FIELD (MNMSKH AND MNMSKL)
Msk28 – Msk18
Msk17 – Msk10
Msk9 – Msk2
Msk1
Msk0
SCREENER ID FIELD (ASSEMBLED FROM INCOMING BIT–STREAM)
CAN ID.28 – CAN ID.18
Data Byte 1 [7:0]
Data Byte 2 [7: 0]
x
x
IDE
NOTE:
1. For a Standard CAN Frame Message Object, only 27 bits plus IDE (11 bits of CAN ID + 2x8 bits + IDE ) from the incoming message are
routed to the acceptance filter. The User is therefore required to set the Msk1 and Msk0 bits in the Mask field for that object (i.e., “don’t
care”). The IDE bit is not Maskable.
In many applications based on Standard CAN frames, either Data
Byte 1, Data Byte 2, or both do not participate in Acceptance
Filtering. Therefore, the User is required to Mask out the unused
Data Byte(s).
OBJECT N MATCH ID FIELD (MNMIDH AND MNMIDL)
Mid28 – Mid18
Mid17 – Mid10
Screener ID Field for Extended CAN Frame
The following table shows how the Screener ID field is assembled
from the incoming bits of an Extended CAN Frame, and how it is
compared to the Match ID and Mask fields of Object n. Note: The
IDE bit is not Maskable.
Mid9 – Mid2
Mid1 Mid0 MIDE
OBJECT N MASK FIELD (MNMSKH AND MNMSKL)
Msk28 – Msk18
Msk17 – Msk10
Msk9 – Msk2
Msk1
Msk0
SCREENER ID FIELD (ASSEMBLED FROM INCOMING BIT–STREAM)
CAN ID.28 – CAN ID.0
IDE
MnMIDH: Message n Match ID High Word
D Address: MMR base + n0h
D Access: Read, write. Word access only.
D Reset value: xxxxh
MNMIDH
15
14
Mid28 Mid27
13
Mid26
12
Mid25
11
Mid24
10
Mid23
9
Mid22
8
Mid21
7
Mid20
6
Mid19
5
Mid18
4
Mid17
3
Mid16
2
Mid15
1
Mid14
0
Mid13
MnMIDL: Message n Match ID Low Word
D Address: MMR base + n2h
D Access: Read, write. Word access only.
MNMIDL
15
14
Mid12 Mid11
13
Mid10
12
11
Mid9 Mid8
10
Mid7
9
Mid6
D Reset value: xxxxxxxxxxxxxx00b (unused bits are always read as
‘0’)
8
7
6
5
4
3
2
1
0
Mid5 Mid4 Mid3 Mid2 Mid1 Mid0 MIDE –
–
MnMSKH: Message n Mask High Word
D Address: MMR base + n4h
MNMSKH
15
14
Msk28 Msk27
13
Msk26
12
Msk25
11
Msk24
10
Msk23
9
Msk22
8
Msk21
D Access: Read, write. Word access only.
D Reset value: xxxxh
7
6
5
4
3
2
Msk20 Msk19 Msk18 Msk17 Msk16 Msk15
1
Msk14
0
Msk13
NOTE:
1. Note: For transmit objects, the frame information is programmed in this register.
MnMSKL: Message n Mask Low Word
D Address: MMR base + n6h
D Access: Read, write. Word access only.
D Reset value: xxxxxxxxxxxxx000b (unused bits are always read as
‘0’)
2000 Jan 25
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