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XA-C3 Datasheet, PDF (14/68 Pages) NXP Semiconductors – XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce | |||
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Philips Semiconductors
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
Preliminary specification
XA-C3
PIN DESCRIPTIONS
Table 4. Pin Descriptions
MNEMONIC
PIN NUMBERS
PLCC
LQFP
VSS
1, 22
16, 39
VDD
23, 44 17, 38
P0.0 â P0.7 43 â 36 37â30
P1.0 â P1.7
2â9
40 â 44
1â3
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
2
40
3
41
4
42
5
43
6
44
7
1
8
2
P1.7
P2.0 â P2.7
9
24 â 31
3
18 â 25
P3.0 â P3.7
11,
13 â 19
5,
7 â12
P3.0
P3.1
P3.2
P3.3
11
5
13
7
14
8
15
9
TYPE
NAME AND FUNCTION
I
Ground: 0V Reference.
I
Power Supply: This is the power supply voltage for normal, Idle and PowerâDown op-
eration.
I/O Port 0: Port 0 is an 8âbit I/O Port with user âconfigurable pins. Port 0 latches have 1âs
written to them and are configured in the QuasiâBidirectional mode during Reset. The
operation of Port 0 pins as inputs or outputs depends upon the Port configuration se-
lected. Each Port pin is configured independently. Refer to the sections on I/O Port
configuration and DC Electrical Characteristics for details.
NOTE:
2. When the External PROGRAM/DATA bus is used, Port 0 becomes the multiplexed
low DATA/Instruction Byte and Address lines 4 through 11.
I/O Port 1: Port 1 is an 8âbit I/O Port with user âconfigurable pins. Port 1 latches have 1âs
written to them and are configured in the QuasiâBidirectional mode during Reset. The
operation of Port 1 pins as inputs or outputs depends upon the Port configuration se-
lected. Each Port pin is configured independently. Refer to the sections on I/O Port
configuration and DC Electrical Characteristics for details.
O WRH/: Address bit 0 of the External Address bus when the External DATA bus is config-
ured for 8âbit width. When the External DATA bus is used, this pin becomes the High
Byte Write Strobe (WRH).
O A1: Address bit 1 of the External Address bus.
O A2: Address bit 2 of the External Address bus.
O A3: Address bit 3 of the External Address bus.
I
SPIRx: Receiver serial input of SPI.
O SPITx: Transmitter serial output of SPI.
I
T2 ; SPICLK: Timer/counter 2 external clock input or Timer/counter 2 ClockâOut mode
output, or SPI Clock output.
NOTES:
3. SPICLK must be configured to idle in the logic â1â state in order to use either the T2
or P1.6 output functions, even if the SPI Port is not in use!
4. The default state from Reset of the SPICLK polarity is âinvertedâ which yields an
SPICLK idle state of logic â1â.
5. If the SPI Clock polarity is changed by the user during SPI Port usage, it must be
restored to âinvertedâ polarity before using either the P1.6 or Timer/counter 2 output
functions.
O T2EX: Timer/counter 2 reload/capture/direction control.
I/O Port 2: Port 2 is an 8âbit I/O port with userâconfigurable pins. Port 2 latches have 1âs
written to them and are configured in the QuasiâBidirectional mode during Reset. The
operation of Port 2 pins as inputs or outputs depends upon the Port configuration se-
lected. Each Port pin is configured independently.
Refer to the sections on I/O port configuration and DC Electrical Characteristics for de-
tails.
NOTES:
6. When the External 16âbit PROGRAM/DATA bus is used, Port 2 is MUXed between
High (DATA/Instruction) Byte and Address lines 12 through 19.
I/O Port 3: Port 3 is an 8âbit I/O Port with userâconfigurable pins.
NOTES:
7. Port 3 latches have 1âs written to them and are configured in the QuasiâBidirectional
mode during Reset.
8. The operation of Port 3 pins as inputs or outputs depends upon the Port
configuration selected.
9. Each Port pin is configured independently.
Refer to the sections on I/O Port configuration and DC Electrical Characteristics for
details.
I
RxD0: Receiver serial input of UART 0.
O TxD0: Transmitter serial output of UART 0.
I
INT0/: External interrupt 0 input.
I
INT1/: External interrupt 1 input.
2000 Jan 25
7
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