XA-C3 Datasheet, PDF (18/68 Pages) NXP Semiconductors – XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce

Philips Semiconductors
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
Preliminary specification
XA-C3
MEMORY-MAPPED REGISTERS
Table 6. Memory-Mapped Registers
Name
Description
Address Offset
Operation
MESSAGE OBJECT REGISTERS (n = 0 – 31)
MnMIDH
MnMIDL
MnMSKH
MnMSKL
MnCTL
MnBLR
MnBSZ
MnFCR
Message n Match ID High
000n₄n₃n₂n₁n₀0000b (n0h) R/W
Message n Match ID Low
000n₄n₃n₂n₁n₀0010b (n2h) R/W
Message n Mask High
000n₄n₃n₂n₁n₀0100b (n4h) R/W
Message n Mask Low
000n₄n₃n₂n₁n₀0110b (n6h) R/W
Message n Control
000n₄n₃n₂n₁n₀1000b (n8h) R/W
Message n Buffer Location
000n₄n₃n₂n₁n₀1010b (nAh) R/W
Message n Buffer Size
000n₄n₃n₂n₁n₀1100b (nCh) R/W
Message n Fragmentation Count
000n₄n₃n₂n₁n₀1110b (nEh) R/W
CAN/CTL INTERRUPT COMPLETE (CIC) REGISTERS
MCPLH
Message Complete Status Flags High 226h
RC
MCPLL
Message Complete Status Flags Low 224h
RC
CANINTFLG CAN Interrupt Flag Register
228h
RC
MCIR
Message Complete Information
229h
RO
MEIR
Message Error Information
22Ah
RO
FEENR
Frame Error Enable
22Eh
R/W
FESTR
Frame Error Status
22Ch
RC
SPI REGISTERS
SPICFG
SPI Configuration
260h
R/W
SPIDATA
SPI Data
262h
R/W
SPICS
CANCMR
SPI Control and Status
CAN Core Command
263h
R/W
CAN CORE BLOCK (CCB) REGISTERS
270h
R/W*
CANSTR
CAN Core Status
271h
RO
CANBTR
CAN Core Bus Timing
272h
R/W*
TxERC
Tx Error Counter
274h
R/W*
RxERC
EWLR
Rx Error Counter
Error Warning Limit
275h
276h
R/W*
R/W
ECCR
Error Code Capture
278h
RO
ALCR
Arbitration Lost Capture
27Ah
RO
GCTL
MIFBTRH
Global Control
27Eh
R/W
MEMORY INTERFACE (MIF) REGISTERS
MIF Bus Timing Register High
293h
R/W
MIFBTRL
MIF Bus Timing Register Low
292h
R/W
MBXSR
Message Buffer and XRAM Segment
Register
291h
R/W
XRAMB
XRAM Base Address
290h
R/W
ACCESS
Word only
Word only
Word only
Word only
Byte
Word only
Byte
Byte
Word
Word
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Word
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Reset Value
xxxxh
x…x00b
xxxxh
x…x000b
00000xxxb
xxxxh
00000xxxb
00xxxxxxb
0000h
0000h
00h
00h
00h
00h
00h
00h
00h
00h
01h (Note 1)
00h
0000h
00h
00h
96h
00h
00h
00h
FFh
EFh
FFh
FEh
Possible Operations: R/W = Read & Write, RO = Read Only, RC = Read then Clear via a service routine, W* = Writable only while the CAN
Core is in Reset mode, x = Undefined after Reset
NOTE:
1. SLPEN (Sleep Enable), CANCMR[3], is writable only when the CAN Core is in Normal mode.
2000 Jan 25
11