XA-C3 Datasheet, PDF (64/68 Pages) NXP Semiconductors – XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce

Philips Semiconductors
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
Preliminary specification
XA-C3
XRAMB
7
6
5
4
3
2
1
0
a15 – a9 of XRAM Base Address
XRE
XRE
MIFCNTL
7
–
XRAM Enable bit, resets to ‘0’.
0 = XRAM disabled
1 = XRAM enabled
6
5
–
–
4
WAITD
MIF Control and Configuration Registers
MIFCNTL (SFR)
D Address: SFR 495h
3
2
1
0
BUSD
–
–
–
WAITD
BUSD
MIFBTRL
7
WM1
Wait Disable
0 = Wail enabled
1 = Wait disabled
External Access Disable
0 = enable
1 = disable
6
WM0
5
ALEW
MIFBTRL (Memory Interface Bus Timing Register Low, MMR)
D Address: MMR base + 292h
D Access: Read, write, byte or word
D Reset value: EFh
4
3
2
1
0
–
CR1
CR0
CRA1
CRA0
MIFBTRH (Memory Interface Bus Timing Register High, MMR)
D Address: MMR base + 294h
MIFBTRH
7
DW1
6
DW0
5
DWA1
4
DWA0
D Access: Read, write, byte or word
D Reset value: FFh
3
DR1
2
DR0
1
DRA1
0
DRA0
Note: The two MMRs MIFBTRL and MIFBTRH are not to be
confused with the two SFRs BTRL and BTRH, which control the
operation of the BIU, not the MIF. In order for the MIF to function
properly, the contents of BTRL and BTRH have to be set at a fixed
configuration on reset, by User application software, similar to the
treatment for the XA-SCC MIF.
Bus Arbitration
Bus arbitration is done on an “alternate” policy. After a DMA bus
access, the CPU will get the bus if requested. After a CPU bus
SPICFG
7
SPCP
6
Rsvd
5
Rsvd
4
Rsvd
access, the DMA will get the bus if requested. A burst access from
the CPU cannot be interrupted by a DMA bus access.
SPI Port
The on–chip SPI Port uses the following Memory Mapped Registers:
SPICFG (MMR)
D Address: MMR base + 260h
D Access: Read, write, byte or word
D Reset value: 00h
3
SPC3
2
SPC2
1
SPC1
0
SPC0
SPCP
Rsvd
SPC3 – SPC0
SPICLK Polarity
0 = inverted SPICLK
1 = normal SPICLK
Reserved bits, only write zeros.
SPICLK timing
SPICLK = (CClk) / 4 (SPICFG[3:0] + 1)
SPIDATA (MMR)
D Address: MMR base + 262h
D Access: Read, write, byte or word
D Reset value: 00h
SPIDATA
7
6
5
4
3
2
1
0
Data
SPICS (MMR)
D Address: MMR base + 263h
D Access: Read, write, byte or word
D Reset value: 00h
2000 Jan 25
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