XA-C3 Datasheet, PDF (36/68 Pages) NXP Semiconductors – XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce

Philips Semiconductors
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
Preliminary specification
XA-C3
V4)
V5)
V6)
V7)
V8)
V9)
V10)
This variable represents the programmed length of an entire code
read cycle with no ALE. This time is determined by the CR1 and
CR0 bits in the BTRL register. V4 = 1 if CR1/0 = 00, 2 if CR1/0 =
01, 3 if CR1/0 = 10, and 4 if CR1/0 = 11.
This variable represents the programmed length of an entire data
read cycle with no ALE. this time is determined by the DR1 and
DR0 bits in the BTRH register. V5 = 1 if DR1/0 = 00, 2 if DR1/0 =
01, 3 if DR1/0 = 10, and 4 if DR1/0 = 11.
This variable represents the programmed length of an entire data
read cycle with ALE. The time is determined by the DRA1 and
DRA0 bits in the BTRH register. V6 = the total bus cycle duration
(2 if DRA1/0 = 00, 3 if DRA1/0 = 01, 4 if DRA1/0 = 10,
and 5 if DRA1/0 = 11).
This variable represents the programmed width of the RD/ pulse
as determined by the DR1 and DR0 bits or the DRA1, DRA0 in the
BTRH register, and the ALEW bit in the BTRL register.
– For a bus cycle with no ALE, V7 = 1 if DR1/0 = 00, 2 if DR1/0
= 01, 3 if DR1/0 = 10, and 4 if DR1/0 = 11.
– For a bus cycle with an ALE, V7 = the total bus cycle duration
(2 if DRA1/0 = 00, 3 if DRA1/0 = 01, 4 if DRA1/0 = 10,
and 5 if DRA1/0 = 11) minus the number of clocks used by
ALE (V1 + 0.5).
Example: If DRA1/0 = 00 and ALEW = 0, then V7 = 2 – (0.5 +
0.5) = 1.
This variable represents the programmed width of the WRL/ and/or
WRH/ pulse as determined by the WM1 bit in the BTRL register.
V8 1 if WM1 = 0, and 2 if WM1 = 1.
This variable represents the programmed address setup time for a
write as determined by the data write cycle duration (defined by
DW1 and DW0 or the DWA1 and DWA0 bits in the BTRH register),
the WM0 bit in the BTRL register, and the value of V8.
– For a bus cycle with an ALE, V9 = the total bus write cycle
duration (2 if DWA1/0 = 00, 3 if DWA1/0 = 01, 4 if DWA1/0 =
10, and
5 if DWA1/0 = 11) minus the number of clocks used by the
WRL/ and/or WRH/ pulse (V8), minus the number of clocks
used by data hold time (0 if WM0 = 0 and 1 if WM0 = 1).
Example: If DWA1/0 = 10, WM0 = 1, and WM1 = 1, then V9 =
4 – 1 – 2 = 1.
– For a bus cycle with no ALE, V9 = the total bus cycle duration
(2 if DW1/0 = 00, 3 if DW1/0 = 01, 4 if DW1/0 = 10, and 5 if
DW1/0 = 11) minus the number of clocks used by the WRL/
and/or WRH/ pulse (V8), minus the number of clocks used by
data hold time (0 if WM0 = 0 and 1 if WM0 = 1).
Example: If DW1/0 = 11, WM0 = 1, and WM1 = 0, then V9 = 5
– 1 – 1 = 3.
This variable represents the length of a bus strobe for calculation
of WAIT setup and hold times. The strobe may be RD/ (for data
read cycles), WRL/ and/or WRH/ (for data write cycles), or PSEN/
(for code read cycles), depending on the type of bus cycle being
widened by WAIT. V10 = V2 for WAIT associated with a code read
cycle using PSEN/. V10 = V8 for a data write cycle using WRL/
and/or WRH/. V10 = V7–1 for a data read cycle using RD/. This
means that a single clock data read cycle cannot be stretched
using WAIT.
If WAIT is used to vary the duration of data read cycles, the RD/
strobe width must be set to be at least two clocks in duration.
Also see Note 4.
V11)
This variable represents the programmed write hold time as
determined by the WM0 bit in the BTRL register.
V11 = 0 if the WM0 bit = 0, and 1 if the WM0 bit = 1.
V12)
This variable represents the programmed period between the end
of the ALE pulse and the beginning of the WRL/ and/or WRH/
pulse as determined by the data write cycle duration (defined by
the DWA1 and DWA0 bits in the BTRH register), the WM0 bit in
the BTRL register, and the values of V1 and V8. V12 = the total
bus cycle duration (2 if DWA1/0 = 00, 3 if DWA1/0 = 01, 4 if
DWA1/0 = 10, and 5 if DWA1/0 = 11) minus the number of clocks
used by the WRL/ and/or WRH/ pulse (V8), minus the number of
clocks used by data hold time (0 if WM0 = 0 and 1 if WM0 = 1),
minus the width of the ALE pulse (V1).
Example: If DWA1/0 = 11, WM0 = 1, WM1 = 0, and ALEW = 1,
then V12 = 5 – 1 – 1 – 1.5 = 1.5.
V13)
This variable represents the programmed data setup time for a
write as determined by the data write cycle duration (defined by
DW1 and DW0 or the DWA1 and DWA0 bits in the BTRH register),
the WM0 bit in the BTRL register, and the values of V1 and V8.
– For a bus cycle with an ALE, V13 = the total bus cycle
duration (2 if DWA1/0 = 00, 3 if DWA1/0 = 01, 4 if DWA1/0 =
10, and 5 if DWA1/0 = 11) minus the number of clocks used by
the WRL/ and/or WRH/ pulse (V8), minus the number of clocks
used by data hold time (0 if WM0 = 0 and 1 if WM0 = 1), minus
the number of clocks used by ALE (V1 + 0.5).
Example: If DWA1/0 = 11, WM0 = 1, WM1 = 1, and ALEW = 0,
then V13 = 5 – 1 – 2 – 1 = 1.
– For a bus cycle with no ALE, V13 = the total bus cycle duration
(2 if DW1/0 = 00, 3 if DW1/0 = 01, 4 if DW1/0 = 10, and 5 if
DW1/0 = 11) minus the number of clocks used by the WRL/
and/or WRH/ pulse (V8), minus the number of clocks used by
data hold time (0 if WM0 = 0 and 1 if WM0 = 1).
Example: If DW1/0 = 01, WM0 = 1, and WM1 = 0, then V13 =
3 – 1 – 1 = 1.
3. Not all combinations of bus timing configuration values result in valid bus
cycles. Refer to the XA User Guide section on the External Bus for details.
4. When code is being fetched for execution on the External bus, a
burst–mode fetch is used that does not have PSEN/ edges in every fetch
cycle. Thus, if WAIT is used to delay code fetch cycles, a change in the
low–order address lines must be detected to locate the beginning of a
cycle. This would be A3 A1 while using an External 16 bit bus.
5. This parameter is provided for peripherals that have the data clocked in on
the falling edge of the WR/ strobe. This is not usually the case, and in
most applications this parameter is not used.
6. Please note that the XA–C3 requires that extended data bus hold time
(WM0 = 1) to be used with External bus write cycles.
2000 Jan 25
29