SAA7385 Datasheet, PDF (6/64 Pages) NXP Semiconductors – Error correction and host interface IC for CD-ROM SEQUOIA

Philips Semiconductors
Error correction and host interface IC for
CD-ROM (SEQUOIA)
Preliminary specification
SAA7385
SYMBOL PIN I/O
PAD
DESCRIPTION
RAS
11
O
S4
DRAM row address section; active LOW
CAS
12
O
S4
DRAM column address selection; active LOW
DWR
13
O
S4
DRAM write; active LOW
DOE
14
O
S4
DRAM output enable; active LOW
V_SS2
DD0
15
−
−
ground 2
16 I/O 4 mA, Schmitt, PD25 DRAM data bus; bit DD0
DD1
17 I/O 4 mA, Schmitt, PD25 DRAM data bus; bit DD1
DD2
18 I/O 4 mA, Schmitt, PD25 DRAM data bus; bit DD2
DD3
19 I/O 4 mA, Schmitt, PD25 DRAM data bus; bit DD3
V_DD2
DD4
20
−
−
power supply 2
21 I/O 4 mA, Schmitt, PD25 DRAM data bus; bit DD4
DD5
22 I/O 4 mA, Schmitt, PD25 DRAM data bus; bit DD5
DD6
23 I/O 4 mA, Schmitt, PD25 DRAM data bus; bit DD6
DD7
V_SS3
LED
24 I/O 4 mA, Schmitt, PD25 DRAM data bus; bit DD7
25
−
−
ground 3
26
O 24 mA, CMOS test panel LED; active LOW; WTGCTL(4)
TRAYSW
27
I
Schmitt, PU25 active LOW when tray is in
EJECT
28
I
Schmitt, PU25 opens tray; active LOW
LQDATA
29
O
2 mA
serial data to DAC
LWCLK
V_SS4
SCLK
30
O
31
−
32
O
2 mA
−
2 mA
word strobe to DAC
ground 4
data serial clock
V_SS5
SYSRES
33
−
34
O
−
2 mA, PU25
ground 5
system reset; OR of POR, SCSIRST and watch-dog timer
CFLAG
35
I
Schmitt, PU400 C1 and C2 status
CPR
36
O
2 mA
S2B interface ready to accept data; active LOW
SPR
37
I
Schmitt
S2B interface ready to send data; active LOW
SKIPFWD
38
I
Schmitt, PU25 skip forwards; active LOW; RDSW(3)
SKIPBACK
39
I
Schmitt, PU25 skip backwards; active LOW; RDSW(2)
SCSICLK
40
I
standard
SCSI interface clock
V_DD3
AD0
41
−
42 I/O
−
S4, Schmitt
power supply 3
microcontroller multiplexed data bus; bit AD0
AD1
43 I/O
S4, Schmitt
microcontroller multiplexed data bus; bit AD1
AD2
44 I/O
S4, Schmitt
microcontroller multiplexed data bus; bit AD2
AD3
45 I/O
S4, Schmitt
microcontroller multiplexed data bus; bit AD3
AD4
46 I/O
S4, Schmitt
microcontroller multiplexed data bus; bit AD4
AD5
47 I/O
S4, Schmitt
microcontroller multiplexed data bus; bit AD5
AD6
48 I/O
S4, Schmitt
microcontroller multiplexed data bus; bit AD6
AD7
49 I/O
S4, Schmitt
microcontroller multiplexed data bus; bit AD7
V_SS6
LA0
50
−
−
ground 6
51
O
CMOS S2, PU25 EPROM latched lower address; bit LA0
1996 Jun 19
6