SAA7385 Datasheet, PDF (20/64 Pages) NXP Semiconductors – Error correction and host interface IC for CD-ROM SEQUOIA

Philips Semiconductors
Error correction and host interface IC for
CD-ROM (SEQUOIA)
Preliminary specification
SAA7385
Table 7 Command execution times
COMMAND
CALCULATE_SYNDROMES (not Mode 2, Form 1)
CALCULATE_SYNDROMES (Mode 2, Form 1)
CRC_RECALCULATE (not Mode 2, Form 1)
CRC_RECALCULATE (Mode 2, Form 1)
COPY_RESULTS (not Mode 2, Form 1)
COPY_RESULTS (Mode 2, Form 1)
CORRECT_P_SYNDROMES
(maximum addition per correction)
CORRECT_Q_SYNDROMES
(maximum addition per correction)
TEST_ECC_RAM_READ
TEST_ECC_RAM_WRITE
CYCLES
5 604
5 600
4 136
4 120
1 148
1 156
1 466
157
888
167
1 184
1 184
TIME (µs)
at 33 MHz
186.8
186.7
137.9
137.3
38.3
38.5
48.9
5.2
29.6
5.6
39.5
39.5
MEMORY
ACCESSES
2 658
2 654
2 068
2 060
574
578
0
2
0
2
592
592
All times indicated reflect two clock cycles per memory access for all accesses other than P and Q corrections. P and Q
corrections reflect seven clock cycles per memory access. Execution times will be extended due to refresh timing, other
buffer traffic, and configuration of nibble-wide memory.
8.3.1 INTERRUPT REGISTER DEFINITIONS
Two registers are used to control the operation of the interrupt logic. The register INTRMSK allows each interrupt to be
enabled or disabled. INTRMSK and INTRFLG are cleared on reset to initially disable and clear all interrupts; the output
latch controlling the INT line is set on a reset; this must be cleared by writing 0x00 to INTRFLG. To enable an interrupt,
the bit that corresponds to the interrupt in INTRFLG must be set. The INTRFLG register shows the status of the
interrupts. If any bit is HIGH then an interrupt has occurred since the last time the bit was cleared. Writing a zero to any
bit location in INTRFLG will clear the corresponding interrupt. If a masked interrupt occurs, the microcontroller can still
detect the occurrence because the event is still posted in INTRFLG.
Table 8 Interrupt mask register: 0xF0FB
MNEMONIC R/W
INTRMSK R/W
7
MASK7
6
MASK6
5
MASK5
DATA BYTE
4
MASK4
3
MASK3
2
MASK2
1
MASK1
0
MASK0
Each bit in register 0xF0FB corresponds to the interrupt at the same bit location in register 0xF0FC. To enable an
interrupt, the bit in this register must be set HIGH.
Table 9 Interrupt flag register: 0xF0FC
MNEMONIC R/W
INTRFLG R/W
DATA BYTE
7
6
5
4
3
2
−
FETXINT FERXINT ECC_COR FE_HDR FE2352
1
0
STR_LST FRM_STR
If any bit is set in this register (Table 9) then an interrupt may be sent to the microcontroller. Table 10 shows when the
interrupts are asserted; assuming the corresponding mask bit is set.
1996 Jun 19
20