SAA7385 Datasheet, PDF (18/64 Pages) NXP Semiconductors – Error correction and host interface IC for CD-ROM SEQUOIA

Philips Semiconductors
Error correction and host interface IC for
CD-ROM (SEQUOIA)
Preliminary specification
SAA7385
Table 5 Definitions of ECC_COMMAND3 to ECC_COMMAND0
EEC_COMMAND
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1100
1101
1110
DESCRIPTION
ASSERT_ABORT
RELEASE_ABORT
CALCULATE_SYNDROMES (not Mode 2, Form 1)
CALCULATE_SYNDROMES (Mode 2, Form 1)
CRC_RECALCULATE (not Mode 2, Form 1)
CRC_RECALCULATE (Mode 2, Form 1)
COPY_RESULTS (not Mode 2, Form 1)
COPY_RESULTS (Mode 2, Form 1)
CORRECT_P_SYNDROMES
CORRECT_Q_SYNDROMES
TEST_ECC_ROM
TEST_ECC_RAM_READ
TEST_ECC_RAM_WRITE
Table 6 Command descriptions
COMMAND
ASSERT_ABORT
RELEASE_ABORT
CRC_RECALCULATE
CALCULATE_SYNDROMES
DESCRIPTION
Terminates any currently active operation and re-initializes the ECC logic. Remains in
reset state until occurrence of the RELEASE_ABORT command. At power-on reset,
the ECC is in the ASSERT_ABORT state. All microcontroller status bits are reset
when the ECC is in the ASSERT_ABORT state.
Terminates the ASSERT_ABORT command and enables activation of other
commands.
Calculate CRC remainder buffer data, storing result in ECC RAM and updating
microcontroller status bit CRC_EQ0. Mode 2, Form 1 uses address 16 : 2075, or
0 : 2067; note 1.
Prepares buffer for correction, calculates P and Q syndromes, and copies error flags
and CRC remainder from buffer to ECC RAM. The microcontroller status bits
PS_EQ0, QS_EQ0 and FLAGS_EQ0 are updated at the end of this operation.
1. Copy header from buffer to ECC RAM (Mode 2, Form 1 only)
2. Write to the buffer.
Not Mode 2, Form 1:
Address 0 → 0x00; Address 1 : 10 → 0xFF; Address 11 → 0x00;
Address 2068 : 2075 → 0x00
Mode 2, Form 1:
Address 0 → 0x00; Add 1 : 10 → 0xFF; Add 11 : 15 → 0x00
3. Read header and frame data from buffer to calculate P and Q syndromes
psyn[0 : 85].s1, psyn[0 : 85].s0, qsyn[0 : 51].s1 and qsyn[0 : 51].s0, storing
results in ECC RAM; see Table 76
4. Copy error flags from buffer to ECC RAM
5. Copy CRC remainder from buffer to ECC RAM
6. Update microcontroller status bits PS_EQ0, QS_EQ0 and FLAGS_EQ0.
1996 Jun 19
18