SAA7385 Datasheet, PDF (33/64 Pages) NXP Semiconductors – Error correction and host interface IC for CD-ROM SEQUOIA

Philips Semiconductors
Error correction and host interface IC for
CD-ROM (SEQUOIA)
Preliminary specification
SAA7385
Table 45 Read status register: 0xF0C3; note 1
MNEMONIC R/W
7
RDDSTAT R DCOTACT
6
BADQ
DATA BYTE
5
4
3
2
1
0
QFRMRDY HDRRDY HDRERR CRCERR DATERR SYNCERR
Note
1. The information in register 0xF0C3 is a copy of the status byte written to the data buffer at the end of every frame.
SYNCERR, DATERR and CRCERR are essentially unusable since they are valid only long enough to be written to
the buffer.
Table 46 RDDSTAT field description
FIELD
SYNCERR
DATERR
CRCERR
HDRERR
HDRRDY
QFRMRDY
BADQ
DCOTACT
LOGIC
0
0
0
0
1
−
−
−
−
DESCRIPTION
Good synchronization detected (valid for 120 ns at the end of a sector).
Good data (valid for 120 ns at the end of a sector).
Good CRC (valid for 120 ns at the end of a sector).
Good header.
If the automatic storage is selected, assertion of HDRERR inhibits data storage.
EFAB during reception of header (valid while HDRRDY set).
If the automatic storage is selected, assertion of HDRERR inhibits data storage.
When set, a valid header is available. If the header is not read within a frame time, this
remains set until the next synchronization pattern and will be set again when the next
header arrives. It is cleared when any of the header bytes are read. This bit generates an
interrupt to the microcontroller when in data mode.
When set, all ten Q-channel bytes are received waiting to be read (BADQ is known). It is
reset at the end of frame or when any of the Q-channel bytes are read. This bit generates an
interrupt to the microcontroller when in audio mode.
If Q-channel information failed CRC then BADQ is set. It is reset on next good CRC check or
on end of frame if DCOACT is running. If DCOACT is not running (i.e. audio mode) BADQ is
reset on next detection of sub-code gap. If AUTOSTR in WTDIR is selected, assertion of
BADQ inhibits audio data storage.
Set when data is being shifted an and stored in the buffer: this will remain HIGH for the
entire transmission.
1996 Jun 19
33