SAA7385 Datasheet, PDF (5/64 Pages) NXP Semiconductors – Error correction and host interface IC for CD-ROM SEQUOIA

Philips Semiconductors
Error correction and host interface IC for
CD-ROM (SEQUOIA)
5 BLOCK DIAGRAM
handbook, full pagewidth
256K × 8 or 1M × 8
DRAM BUFFER
Preliminary specification
SAA7385
CD
DECODER
data subcode
DATA
CONVERTER
AND SUB-CODE
UART
data
subcode
C-flag
BUFFER MANAGER
LAYERED
ERROR
CORRECTOR
BUFFER
MAPPER
53CF94
SCSI
MICROCONTROLLER INTERFACE
SCSI
interface
SERVO
PROCESSOR
S2B serial interface
SAA7385
80C32 MICROCONTROLLER
DEBUG UART
debug
UART
64K × 8 ROM
MGE388
Fig.1 Block diagram (simplified).
6 PINNING
All input, output and bidirectional signals are TTL level unless otherwise stated (Pull-Down = PD25 = 25 µA;
Pull-Up = PU25 = 25 µA, PU400 = 400 µA; Slew = S2 = 2 mA, S4 = 4 mA;
CMOS slew = CMOS S2 = CMOS 2 = 2 mA; SCSI pad = SCSI = 48 mA).
SYMBOL PIN I/O
DA2
1
O
DA3
2
O
DA4
3
O
V_SS1
DA5
4
−
5
O
DA6
6
O
DA7
7
O
DA8
8
O
DA9
9
O
V_DD1
10
−
PAD
S4
S4
S4
−
S4
S4
S4
S4
S4
−
DESCRIPTION
DRAM address bus; bit DA2
DRAM address bus; bit DA3
DRAM address bus; bit DA4
ground 1
DRAM address bus; bit DA5
DRAM address bus; bit DA6
DRAM address bus; bit DA7
DRAM address bus; bit DA8
DRAM address bus; bit DA9
power supply 1
1996 Jun 19
5