SAA7385 Datasheet, PDF (43/64 Pages) NXP Semiconductors – Error correction and host interface IC for CD-ROM SEQUOIA

Philips Semiconductors
Error correction and host interface IC for
CD-ROM (SEQUOIA)
Preliminary specification
SAA7385
Table 72 Test Register: 0xF06 - 53CF94 address 0x0A; note 1
DATA BYTE
MNEMONIC R/W
7
6
5
4
3
2
1
0
TEST
R/W
−
−
−
−
−
HI-Z
INIT
TAR
Note
1. This register is enabled by setting the test mode in CONFIG1; after test mode is entered, a hardware reset or reset
command must occur before normal operation may resume.
Table 73 TEST field descriptions
FIELD
TAR
INIT
HI-Z
target mode
initiator mode
all outputs set to high impedance
DESCRIPTION
Table 74 FIFO Bottom: 0xFBF - 53CF94 address 0x0F; note 1
DATA BYTE
MNEMONIC R/W
7
6
5
4
3
2
1
0
FIFOBTM
W DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
Note
1. This register is used during initiator synchronous data in to align 16-bit DMA transfers to word boundaries.
1996 Jun 19
43