SAA7385 Datasheet, PDF (12/64 Pages) NXP Semiconductors – Error correction and host interface IC for CD-ROM SEQUOIA

Philips Semiconductors
Error correction and host interface IC for
CD-ROM (SEQUOIA)
Preliminary specification
SAA7385
7.4.4 C-FLAG RECEIVER
The C-flag bits, or corrector flags, are also 24 data clocks
long and reception of these bits is achieved using the
same method as for the sub-code; in this event, the C-flag
data is synchronized to the data. The difference is that only
one bit is used; F1, the absolute time synchronization
information. When in audio mode and ENABRED in
FECTL is set, receipt of F1 set will start the internal data
clock after the next rising edge of word strobe (WSAB)
which is the left channel sample when the CD decoder is
programmed for EIAJ audio format. When in audio mode,
the Q-channel information provides the MSF address and
the F1 flag provides the start of frame information; together
these provide an absolute byte address on the disc.
7.4.5 S2B UART
This UART is provided for remote debugging of the
firmware. It is hard-wired for one start-bit, eight data bits,
a parity bit and one stop bit. Parity testing can be
programmed to be either odd parity or even parity. Parity
error and over-run status are provided via PE and
OVRRUN in S2BSTAT. Selectable baud rates of 31.25,
62.5 and 187.5 kbaud are available via ICESEL1 and
ICESEL0 in BRGSEL.
7.4.6 WATCH-DOG TIMER
A pair of counters are included which output a 967 µs reset
pulse to the entire chip and the SYSRES pin if the timer is
not reset during the 212 ms time-out period.
The watch-dog timer is reset by setting RWMD in FECTL
HIGH then LOW. If RWMD is left HIGH, the watch-dog
function is disabled.
7.4.7 GLUE LOGIC (GLIC)
The final block of logic in the front-end consists of:
a programmable, linear pulse-width modulator for
spindle-motor control; an address de-multiplexer for the
address/data bus of the microcontroller; plus audio
multiplexing and muting circuitry for full control of Red
Book audio data to an external Digital-to-Analog Converter
(DAC).
7.4.8 BUFFER MANAGER
The buffer manager provides the arbitration for the
different processes that wish to access the DRAM buffer.
These processes include the front-end, microcontroller
requests, ECC accesses, SCSI interface requests and
DRAM refreshing. The DRAM control logic will start an
access on the next rising edge of the clock after a request
is received. If two or more requests are pending then the
priority is as follows:
1. Front-end (highest priority)
2. Microcontroller requests
3. SCSI interface requests
4. ECC requests (lowest priority).
A refresh cycle is required every 15.6 µs and will be
granted priority for one access. A burst access by ECC or
SCSI will only be interrupted by a higher priority access
request.
In addition to the priority logic, logic is required for the
front-end sources of data. The priority is: frame data
(highest), flag data, sub-code data, Q-channel data and
finally status byte. All front-end sources are granted
priority over the SCSI logic, ECC, refresh and data will be
written into the frame store during the next cycle. However,
the microcontroller has priority over the lower three
front-end sources and will be granted an access after
front-end frame data or flag data is written to memory.
The required timing (see Figs 4 to 11) operate with the
industry standard 70 ns DRAMs. The interface is designed
to operate with one or two DRAMs using: 256 kbit × 4 or
1 Mbit × 4 devices. If a single DRAM is connected, all
access cycles require a page mode cycle to load both the
high and the low nibble of data. With a byte-wide memory
attached, a single byte cycle takes five clock cycles of
29.5 ns each, totalling 147.5 ns. In nibble mode, a single
byte cycle takes 236 ns.
1996 Jun 19
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