SAA7385 Datasheet, PDF (30/64 Pages) NXP Semiconductors – Error correction and host interface IC for CD-ROM SEQUOIA

Philips Semiconductors
Error correction and host interface IC for
CD-ROM (SEQUOIA)
Preliminary specification
SAA7385
Table 38 DRAM selection/test mode: 0xF0FE; note 1
MNEMONIC R/W
DRAMSEL R/W
7
TEST
DATA BYTE
6
5
4
3
RESTEST3 to RESTEST0
2
1
0
DBL_SPD 1_MEG 2_DRAMS
Note
1. After power-up or reset, DRAMSEL should be the first register that is programmed. This register is used to select the
number and the type of DRAMs used. The output of this register is used to control the DRAM access directly and will
affect any current DRAM cycle.
Table 39 SCSIMOD field description
FIELD
2_DRAMS
1_MEG
DBL_SPD
RESTEST3
to
RESTEST0
TEST
LOGIC
DESCRIPTION
0 single DRAM used
1 two DRAMs used
0 256 k × 4
1 1M×4
0 single speed refresh; condition after reset
1 double speed refresh; only set if system is running at 0.5 master clock speed
− reserved for test: enable DRAM access test; switch multiplexer control, enable interrupts
0 normal operation
1 test mode; read back of RESTEST3 to RESTEST0 is gated by this bit
1996 Jun 19
30