SAA7385 Datasheet, PDF (50/64 Pages) NXP Semiconductors – Error correction and host interface IC for CD-ROM SEQUOIA

Philips Semiconductors
Error correction and host interface IC for
CD-ROM (SEQUOIA)
Preliminary specification
SAA7385
15.3 R-W timing (see Fig.15)
The data from sub-code R-W may be read via the V4 pin
from the CD-decoder and has a format similar to RS232.
The sub-code synchronization word is formatted by a
pause of 200 µs minimum. Each sub-code byte starts with
a logic 1 followed by seven bits (Q to W). The gap between
bytes is variable between 1.3 and 90 µs.
15.4 C-flag timing (see Fig.16)
A 1-bit flag signal is input to the CFLAG pin. This signal
shows the status of the error corrector and interpolator and
is updated every frame.
handbook, full pagewidth
W96
200 µs min
11.3
µs
1 Q1 R1 S1 T1 U1 V1 W1
11.3 µs min
90 µs max
1
MGE401
Fig.15 Sub-code formatting and timing from the V4 pin.
handbook, full pagewidth
1996 Jun 19
11.3
µs
F1 F2 F3 F4 F5 F6 F7
45.4 µs
(nominal speed)
MGE402
Fig.16 C-flag output timing.
50