SAA7385 Datasheet, PDF (41/64 Pages) NXP Semiconductors – Error correction and host interface IC for CD-ROM SEQUOIA

Philips Semiconductors
Error correction and host interface IC for
CD-ROM (SEQUOIA)
Preliminary specification
SAA7385
Table 65 SEQSTP field descriptions
FIELD
DESCRIPTION
SS2 to SS0
Sequence step. Counter increments at various points in a command; may be used for error
recovery.
SOM
Synchronous offset maximum. When clear, the synchronous offset has reached the maximum
value.
TRANSPERIOD Synchronous transfer period. Specifies minimum time between successive REQ or ACK pulses.
Table 66 FIFO flags and synchronous offset register: 0xF0AF - 53CF94 address 0x07; note 1
DATA BYTE
MNEMONIC R/W
7
6
5
4
3
2
1
0
FIFOFLG
R
SS2
SS1
SS0
FF4
FF3
FF2
FF1
FF0
FIFOFLG
W
SYNCOFFSET7 to SYNCOFFSET0
Note
1. The field description for the FIFO flags register is shown in Table 67.
Table 67 FIFOFLG field descriptions
FIELD
FF
SS
SYNCOFFSET
DESCRIPTION
number of bytes in the FIFO
duplicates of sequence step register
controls handshaking in synchronous transfer mode
Table 68 Configuration registers: 0xF0B4, F0B7, F0BC and F0BD - 53CD94 addresses 0x08, 0B, 0C and 0D; note 1
MNEMONIC
CONFIG1
CONFIG2
CONFIG3
CONFIG4
R/W
7
R/W SLOW
R/W RFB
R/W IMRC
R/W
−
6
SRD
FE
QTE
−
5
PTEST
EBC
CDB10
−
DATA BYTE
4
PCHK
DHZ
FSCSI
−
3
CTEST
SCSI2
FCLK
−
2
1
0
MYBUSID2 to MYBUSID0
BPA
RPE
DPE
SRB ADMA
T8
EAN
TEST BBTE
Note
1. The registers described allows the controller to be configured for the specific mode of operation.
1996 Jun 19
41