SAA7385 Datasheet, PDF (28/64 Pages) NXP Semiconductors – Error correction and host interface IC for CD-ROM SEQUOIA

Philips Semiconductors
Error correction and host interface IC for
CD-ROM (SEQUOIA)
Preliminary specification
SAA7385
Table 31 BRGSEL field description
FIELD
LOGIC
DESCRIPTION
ICESEL1 to 0 00 31.25 kbaud transfer rate
01 62.5 kbaud transfer rate
10 187.5 kbaud transfer rate
11 not specified
INVQ
− inverts all Q-channel information if set
INVSUBC
− inverts all sub-code information if set
EVENPAR
LOCK
− selects even parity for S2B UART is set
− read only information; indicates clock synthesizer is stable (after reset) and it is ready to set
C_34_16
C_34_16
− once LOCK is HIGH, asserting this bit engages the clock doubler
Table 32 UART special control register: 0xF09E; note 1
MNEMONIC R/W
7
DATA BYTE
6
5
4
3
2
1
0
UARTCTL R/W EXTUART UARTCNT DIVIDE5 DIVIDE4 DIVIDE3 DIVIDE2 DIVIDE1 DIVIDE0
Note
1. Register 0xF09E allows the 80C32 UART clock to be derived from 16.945 MHz. This external UART clock is required
for reliable operation of the UART if the 80C32 is used for other functions during the transfer.
Table 33 UARTCTL field description
FIELD
DIVIDE5 to 0
UARTCNT
EXTUART
LOGIC
DESCRIPTION
− value 0 produces a 0.264 MHz clock and 58 produces a 2.82 MHz clock for the UART; this is
the maximum accepted by the 80C32, a smaller number is required for guaranteed
operation e.g. 15
0 normal UART data input sampled by the external clock
1 select a UART data input sampled by the clock from the internal counter
0 use external UART clock; disables internal clock
1 switch external UART clock input from pin to this internal counter
1996 Jun 19
28