SAA7385 Datasheet, PDF (2/64 Pages) NXP Semiconductors – Error correction and host interface IC for CD-ROM SEQUOIA

Philips Semiconductors
Error correction and host interface IC
for CD-ROM (SEQUOIA)
CONTENTS
11
1
FEATURES
11.1
11.2
1.1
General
11.3
1.2
53CF94 SCSI controller
11.4
1.3
80C32 high-speed microcontroller
11.5
1.4
Front-end interface logic
11.6
1.5
Buffer controller
1.6
Hardware third-level error correction
12
1.7
Additional product support
13
2
GENERAL DESCRIPTION
14
3
QUICK REFERENCE DATA
15
4
ORDERING INFORMATION
15.1
5
BLOCK DIAGRAM
15.2
15.3
6
PINNING
15.4
7
FUNCTIONAL DESCRIPTION
15.5
7.1
80C32 microcontroller
15.6
7.2
53CF94 fast SCSI controller
15.7
7.3
Input clock doubler
15.8
7.4
Front-end
8
MICROCONTROLLER INTERFACE
16
8.1
Microcontroller interface status register
17
8.2
Microcontroller interface command register
17.1
8.3
Microcontroller interrupts
17.2
8.4
Microcontroller RAM organization
17.3
9
FRONT PANEL AND MISCELLANEOUS
17.4
CONTROL SIGNALS
18
9.1
S2B UART registers
19
9.2
Miscellaneous control registers
10
FRONT-END
10.1
Minute Second Frame (MSF) addressing and
header information
10.2
Front-end status and control
Preliminary specification
SAA7385
BUFFER MANAGER
Front-end to buffer manager interface
Microcontroller to buffer manager interface
ECC to buffer manager interface
SCSI to buffer manager interface
Miscellaneous buffer manager considerations
53CF94 related registers
FRAME BUFFER ORGANIZATION
SUMMARY OF CONTROL REGISTER MAP
LIMITING VALUES
OPERATING CHARACTERISTICS
I²S-bus timing; data mode
EIAJ timing; audio mode
R-W timing (see Fig.15)
C-flag timing (see Fig.16)
S2B interface timing
SCSI interface timing
Microprocessor interface
DRAM interface (the SAA7385 is designed to
operate with standard 70 ns DRAMs)
PACKAGE OUTLINE
SOLDERING
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
DEFINITIONS
LIFE SUPPORT APPLICATIONS
1996 Jun 19
2