SAA7385 Datasheet, PDF (48/64 Pages) NXP Semiconductors – Error correction and host interface IC for CD-ROM SEQUOIA

Philips Semiconductors
Error correction and host interface IC for
CD-ROM (SEQUOIA)
Preliminary specification
SAA7385
15.2 EIAJ timing; audio mode
V_DD = 4.75 to 5.25 V; V_SS = 0 V; T_amb = −10 to +70 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
EIAJ timing (single speed × n); see Fig.14 and note 1
CLOCK INPUT: CLAB
T_cy
output clock period
sample rate = f_s
−
472.4/n
−
ns
sample rate = 2 f_s
−
236.2/n
−
ns
sample rate = 4 f_s
−
118.1/n
−
ns
t_CH
clock HIGH time
sample rate = f_s
166/n
−
−
ns
sample rate = 2f_s
83/n
−
−
ns
sample rate = 4f_s
42/n
−
−
ns
t_CL
clock LOW time
sample rate = f_s
166/n
−
−
ns
sample rate = 2f_s
83/n
−
−
ns
sample rate = 4f_s
42/n
−
−
ns
INPUTS: DAAB, WSAB AND EFAB
t_su
set-up time
t_h
hold time
sample rate = f_s
95/n
−
sample rate = 2f_s
48/n
−
sample rate = 4f_s
24/n
−
sample rate = f_s
95/n
−
sample rate = 2f_s
48/n
−
sample rate = 4f_s
24/n
−
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
Note
1. The EIAJ timing is directly related to the overspeed factor ‘n’ in the normal operating mode. In the lock-to-disc mode
‘n’ is replaced by the disc speed factor ‘d’.
1996 Jun 19
48