ASX340AT_16 Datasheet, PDF (6/54 Pages) ON Semiconductor – 1/4‐inch Color CMOS NTSC/PAL Digital Image SOC

PIN DESCRIPTIONS AND ASSIGNMENTS
TABLE 3. PIN DESCRIPTION
Pin Number
Clock and Reset
A2
Pin Name
EXTCLK
B1
XTAL
D2
RESET_BAR
E1
FRAME_SYNC
Register Interface
F1
F2
E2
SCLK
SDATA
SADDR
SPI Interface
D4
SPI_SCLK
E4
SPI_SDI
H3
SPI_SDO
H2
SPI_CS_N
(Parallel) Pixel Data Output
F7
FRAME_VALID
G7
LINE_VALID
E6
PIXCLK
F8, D6, D7, C6, C7, B6, B7, A6
DOUT[7:0]
B3
DOUT_LSB1
C2
DOUT_LSB0
ASX340AT
Type
Input
Output
Input
Input
Input
Input/Output
Input
Output
Input
Output
Output
Input/Output
Input/Output
Output
Output
Input/Output
Input/Output
Description
Master input clock (27 MHz): This can either be a
square-wave generated from an oscillator (in which
case the XTAL input must be left unconnected) or
connected directly to a crystal.
If EXTCLK is connected to one pin of a crystal, this
signal is connected to the other pin; otherwise this
signal must be left unconnected.
Asynchronous active-low reset: When asserted, the
device will return all interfaces to their reset state.
When released, the device will initiate the boot
sequence. This signal has an internal pull-up resistor.
This input can be used to set the output timing of the
ASX340AT to a fixed point in the frame.
The input buffer associated with this input is
permanently enabled. This signal must be connected
to GND if not used.
These two signals implement the serial
communications protocol for access to the internal
registers and variables.
This signal controls the device ID that will respond to
serial communication commands.
Two-wire serial interface device ID selection:
0: 0x90
1: 0xBA
Clock output for interfacing to an external SPI memory
such as Flash/EEPROM. Tri-state when RESET_BAR
is asserted.
Data in from SPI device. This signal has an internal
pull-up resistor.
Data out to SPI device. Tri-state when RESET_BAR is
asserted.
Chip selects to SPI device. Tri-state when
RESET_BAR is asserted.
Pixel data from the ASX340AT can be routed out on
this interface and processed externally.
To save power, these signals are driven to a constant
logic level unless the parallel pixel data output or
alternate (GPIO) function is enabled for these pins.
This interface is disabled by default.
The slew rate of these outputs is programmable.
These signals can also be used as general purpose
input/outputs.
When the sensor core is running in bypass mode, it
will generate 10 bits of output data per pixel. These
two pins make the two LSB of pixel data available
externally. Leave DOUT_LSB1and DOUT_LSB0
unconnected if not used. To save power, these signals
are driven to a constant logic level unless the sensor
core is running in bypass mode or the alternate
function is enabled for these pins. The slew rate of
these outputs is programmable.
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