ASX340AT_16 Datasheet, PDF (51/54 Pages) ON Semiconductor – 1/4‐inch Color CMOS NTSC/PAL Digital Image SOC

ASX340AT
TABLE 50. TWO-WIRE SERIAL BUS CHARACTERISTICS
(f_EXTCLK = 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V;
VDD_PLL = 2.8 V; VDD_DAC = 2.8 V; T_A = 25°C)
Standard Mode
Fast Mode
Parameter
Symbol
Min
Max
Min
Max
Units
After this period, the first clock
t_HD;STA
4.0
−
pulse is generated
0.6
−
ms
LOW period of the SCLK clock
t_LOW
4.7
−
1.3
−
ms
HIGH period of the SCLK clock
t_HIGH
4.0
−
0.6
−
ms
Se-up time for a repeated START
t_SU;STA
4.7
condition
−
0.6
−
ms
Data hold time
t_HD;DAT
0⁴
Data set-up time
t_SU;DAT
250
Rise time of both SDATA and SCLK
t_r
−
signals
3.45⁵
−
1000
0⁶
100⁶
20 + 0.1Cb⁷
0.9⁵
ms
−
ns
300
ns
Fall time of both SDATA and SCLK
t_f
−
signals
300
20 + 0.1Cb⁷
300
ns
Set-up time for STOP condition
t_SU;STO
4.0
−
0.6
−
ms
Bus free time between a STOP
t_BUF
4.7
−
1.3
−
ms
and START condition
Capacitive load for each bus line
C_b
−
400
Serial interface input pin
C_{IN_SI}
−
3.3
capacitance
−
400
pF
−
3.3
pF
SDATA max load capacitance
C_{LOAD_SD}
−
30
−
30
pF
SDATA pull-up resistor
R_SD
1.5
4.7
1.5
4.7
KW
1. This table is based on I²C standard (v2.1 January 2000). Philips Semiconductor.
2. Two-wire control is I²C-compatible.
3. All values referred to V_IHmin = 0.9 VDD and V_ILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz.
4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK.
5. The maximum t_HD;DAT has only to be met if the device does not stretch the LOW period (t_LOW) of the SCLK signal.
6. A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement t_SU;DAT 250 ns must then be met. This
will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW period
of the SCLK signal, it must output the next data bit to the SDATA line t_r max + t_SU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode
I²C-bus specification) before the SCLK line is released.
7. Cb = total capacitance of one bus line in pF.
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