ASX340AT_16 Datasheet, PDF (36/54 Pages) ON Semiconductor – 1/4‐inch Color CMOS NTSC/PAL Digital Image SOC

ASX340AT
Figure 31 shows detailed vertical blanking information
for PAL timing. See Table 25 for data on field, vertical
blanking, EAV, and SAV states.
Field 1
(F = 0)
Odd
Blanking
Field 1 Active Video
Line 1 (V = 1)
Line 2 3 (V = 0)
Field 2
(F =
n
Blanking
Field 2 Active Vi deo
Line 311 (V = 1)
Line 336 (V = 0)
Blanking
Line 62 4 (V = 1)
Line 625 (V = 1)
H = H=
Figure 36. Typical CCIR656 Vertical Blanking Intervals for 625/50 Video System
TABLE 28. FIELD, VERTICAL BLANKING, EAV, AND SAV STATES FOR 625/50 VIDEO SYSTEM
Line Number
F
V
H (EAV)
1–22
0
1
1
23–310
0
0
1
311–312
0
1
1
313–335
1
1
1
336–623
1
0
1
624–625
1
1
1
H (SAV)
0
0
0
0
0
0
Reset and Clocks
Reset
Power-up reset is asserted or de-asserted with the
RESET_BAR pin, which is active LOW. In the reset state,
all control registers are set to default values. See “Device
Configuration” for more details on Auto, Host, and Flash
configurations.
Soft reset is asserted or de-asserted by the two-wire serial
interface. In soft-reset mode, the two-wire serial interface
and the register bus are still running. All control registers are
reset using default values.
Clocks
The ASX340AT has two primary clocks:
• A master clock coming from the EXTCLK signal.
• In default mode, a pixel clock (PIXCLK) running at
2 * EXTCLK. In raw Bayer bypass mode, PIXCLK
runs at the same frequency as EXTCLK.
When the ASX340AT operates in raw Bayer bypass
mode, the image flow pipeline clocks can be shut off to
conserve power.
The sensor core is a master in the system. The sensor core
frame rate defines the overall image flow pipeline frame
rate. Horizontal blanking and vertical blanking are
influenced by the sensor configuration, and are also a
function of certain image flow pipeline functions. The
relationship of the primary clocks is depicted in Figure 32.
www.onsemi.com
36