ASX340AT_16 Datasheet, PDF (39/54 Pages) ON Semiconductor – 1/4‐inch Color CMOS NTSC/PAL Digital Image SOC

ASX340AT
NTSC Block
VDD_DAC
DAC_REF Pad
ESD
Resistor
2.35 kW
ESD
Pad DAC_POS
Pad DAC_NEG
ESD
GND
NOTE: All I/O circuitry shown above is for reference only. The actual implementation may be different.
Figure 39. NTSC Block
SDATA
Input/output
Pad
Pad
VDD_I0
Receiver
Transmitter
GND
Figure 40. Serial interface
I/O Timing
Digital Output
By default, the ASX340AT launches pixel data, FV, and
LV synchronously with the falling edge of PIXCLK. The
expectation is that the user captures data, FV, and LV using
the rising edge of PIXCLK. The timing diagram is shown in.
Input
EXTCLK
As an option, the polarity of the PIXCLK can be inverted
from the default by programming R0x0016[14].
t_{extclk_period}
Output
PIXCLK
Output
DOUT [7:0]
Output FRAME_VALID
LINE_VALID
t _{pixclkf_dout}
t
dout_ho
t _{pixclkf_fvlv}
t
dout_su
t_{fvlv_su}
Figure 41. Digital Output I/O Timing
t
fvlv_ho
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