ASX340AT_16 Datasheet, PDF (41/54 Pages) ON Semiconductor – 1/4‐inch Color CMOS NTSC/PAL Digital Image SOC

ASX340AT
Configuration Timing
During start-up, the Dout_LSB0, LV and FV are sampled.
Setup and hold timing for the RESET_BAR signal with
respect to DOUT_LSB0, LV, and FV are shown in Figure 38
and Table 30. These signals are sampled once by the on-chip
firmware, which yields a long ^tHOLD time.
RESET_BAR
tSETUP tHOLD
LINE_VALID
Valid Data
Figure 43. Configuration Timing
TABLE 33. CONFIGURATION TIMING
Signal
Parameter
Min
Typ
Max
Units
DOUT_LSB0, FRAME_VALID,
t_SETUP
0
μs
LINE_VALID
t_HOLD
50
μs
1. Table data is based on EXTCLK = 27 MHz.
VDD_PLL
VDD_DAC (2.8)
VAA_PIX
VAA (2.8)
V ^{DD_IO (2.8)}
t0
t1
t2
VDD (1.8)
EXTCLK
RESET_BAR
t3
Hard Reset
t4
Internal
Initialization
Figure 44. Power Up Sequence
t5
Patch Config
SPI or Host
Streaming
TABLE 34. POWER UP SEQUENCE
Definition
Symbol
Min
Typical
Max
Unit
VDD_PLL to VAA/VAA_PIX
t0
0
–
–
ms
VAA/VAA_PIX to VDD_IO
t1
0
–
–
ms
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