ASX340AT_16 Datasheet, PDF (10/54 Pages) ON Semiconductor – 1/4‐inch Color CMOS NTSC/PAL Digital Image SOC

ASX340AT
SOC DESCRIPTION
Detailed Architecture Overview
Sensor Core
The sensor consists of a pixel array, an analog readout
chain, a 10-bit ADC with programmable gain and black
offset, and timing and control as illustrated in Figure 4.
Array
Control Register
Communication
Timing and Control
Clock
Analog Processing
ADC
10−Bit Data
to IFP
Figure 4. Sensor Core Block Diagram
Pixel Array Structure:
The sensor core pixel array is configured as 728 columns
by 560 rows, as shown in Figure 5.
lens alignment rows
demosaic rows
(40, 36) (0, 0)
Pixel logical address = (0, 0)
Active pixel array
640 x 480
Pixel logical address = (727, 559)
demosaic rows
lens alignment rows
(687, 523)
(not to scale)
Figure 5. Pixel Array Description
Black rows used internally for automatic black level
adjustment are not addressed by default, but can be read out
in raw output mode via a register setting.
There are 728 columns by 560 rows of optically-active
pixels (that is, clear pixels) that include a pixel boundary
around the VGA (640 x 480) image to avoid boundary
effects during color interpolation and correction. Among the
728 columns by 560 rows of clear pixels, there are 36 lens
alignment rows on the top and bottom, and 40 lens alignment
columns on the left and right; and there are 4 demosaic rows
and 4 demosaic columns on each side.
Figure 6 illustrates the process of capturing the image.
The original scene is flipped and mirrored by the sensor
optics. Sensor readout starts at the lower right corner. The
image is presented in true orientation by the output display.
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