ASX340AT_16 Datasheet, PDF(37/54 Page) ON Semiconductor – 1/4‐inch Color CMOS NTSC/PAL Digital Image SOC

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ASX340AT_16 Datasheet, PDF (37/54 Pages) ON Semiconductor – 1/4‐inch Color CMOS NTSC/PAL Digital Image SOC

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ASX340AT

The image flow pipeline typically generates up to 16 bits

per pixel â for example, YCbCr or 565RGB â but has only

an 8-bit port through which to communicate this pixel data.

To generate NTSC or PAL format images, the sensor core

requires a 27 MHz clock.

EXTCLK

Sensor

Master Clock

Sensor

Pixel Clock

Sensor Core

10 bits/pixel

1 pixel/clock

Colorpipe

16 bits/pixel

1 pixel/clock

Output Interface

16 bits/pixel (TYP)

0.5 pixel/clock

Figure 37. Primary Clock Relationships

Floating Inputs

The following ASX340AT pins cannot be floated:

â¢ SDATAâThis pin is bidirectional and should not be

floated

â¢ FRAME_SYNC

â¢ TRST_N

â¢ SCLK

â¢ SADDR

â¢ ATEST1

â¢ ATEST2

Output Data Ordering

TABLE 29. EIA COLOR BARS (NTSC)

Mode

(Swap Disabled) Byte

565RGB

First

Second

555RGB

First

Second

444xRGB

First

Second

x444RGB

First

Second

1. PIXCLK is 54 MHz when EXTCLK is 27 MHz.

TABLE 30. EIA COLOR BARS (NTSC)

Mode

DOUT_LSB1 DOUT_LSB0

10-bit Output

1. PIXCLK is 27 MHz when EXTCLK is 27 MHz.

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