ASX340AT_16 Datasheet, PDF (26/54 Pages) ON Semiconductor – 1/4‐inch Color CMOS NTSC/PAL Digital Image SOC

ASX340AT
TABLE 21. PATCH LOADER HOST COMMANDS
Patch Loader Host
Command
Value
Load Patch
0x8700
Type
Asynchronous
Status
0x8701
Synchronous
Apply Patch
Reserve RAM
0x8702
0x8706
Asynchronous
Synchronous
Description
Load a patch from SPI Flash and automatically
apply
Get status of an active Load Patch or Apply Patch
request
Apply a patch (already located in Patch RAM)
Reserve RAM to contain a patch
TABLE 22. MISCELLANEOUS HOST COMMANDS
Miscellaneous Host
Command
Value
Invoke Command Seq
0x8900
Config Command Seq
Processor
0x8901
Wait For Event
0x8902
Type
Synchronous
Synchronous
Synchronous
Description
Invoke a sequence of commands stored in NVM
Configures the Command Sequencer processor
Wait for a system event to be signalled
TABLE 23. CALIBRATION STATS HOST COMMANDS
Calibration Stats Host
Command
Value
Type
Control
0x8B00
Asynchronous
Read
0x8B01
Synchronous
Description
Start statistics gathering
Read the results back
SLAVE TWO-WIRE SERIAL INTERFACE
The two-wire serial interface bus enables read/write
access to control and status registers within the ASX340AT.
This interface is designed to be compatible with the MIPI
Alliance Standard for Camera Serial Interface 2 (CSI-2) 1.0,
which uses the electrical characteristics and transfer
protocols of the two-wire serial interface specification.
The interface protocol uses a master/slave model in which
a master controls one or more slave devices. The sensor acts
as a slave device. The master generates a clock (SCLK) that
is an input to the sensor and used to synchronize transfers.
Data is transferred between the master and the slave on a
bidirectional signal (SDATA). SDATA is pulled up to VDD_IO
off-chip by a pull-up resistor in the range of 1.5 to 4.7 kΩ.
Protocol
Data transfers on the two-wire serial interface bus are
performed by a sequence of low-level protocol elements, as
follows:
• a start or restart condition
• a slave address/data direction byte
• a 16-bit register address
• an acknowledge or a no-acknowledge bit
• data bytes
• a stop condition
The bus is idle when both SCLK and SDATA are HIGH.
Control of the bus is initiated with a start condition, and the
bus is released with a stop condition. Only the master can
generate the start and stop conditions.
The SADDR pin is used to select between two different
addresses in case of conflict with another device. If SADDR
is LOW, the slave address is 0 x 90; if SADDR is HIGH, the
slave address is 0 x BA. See Table 21.
TABLE 24. TWO-WIRE INTERFACE ID ADDRESS
SWITCHING
SADDR
Two-Wire Interface Address ID
0
0x90
1
0xBA
Start Condition
A start condition is defined as a HIGH-to-LOW transition
on SDATA while SCLK is HIGH. At the end of a transfer, the
master can generate a start condition without previously
generating a stop condition; this is known as a “repeated
start” or “restart” condition.
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