ASX340AT_16 Datasheet, PDF (42/54 Pages) ON Semiconductor – 1/4‐inch Color CMOS NTSC/PAL Digital Image SOC

ASX340AT
TABLE 34. POWER UP SEQUENCE (CONTINUED)
Definition
Symbol
Min
Typical
Max
Unit
VDD_IO to VDD
t2
0
–
–
ms
Hard Reset
t3
2
–
–
ms
Internal Initialization
t4
14
–
–
ms
1. Delay between VDD and EXTCLK depends on customer devices, i.e. Xtal, Oscillator, and so on. There is no requirement on this from the
sensor.
2. Hard reset time is the minimum time required after power rails are settled. Ten clock cycles are required for the sensor itself, assuming all
power rails are settled. In a circuit where Hard reset is performed by the RC circuit, then the RC time must include the all power rail settle
time and Xtal.
3. The time for Patch Config SPI or Host, that is, t5, depends on the patches being applied.
VDD (1.8)
VDD_IO (2.8)
V
AA (2.8)
V
DD_DAC (2.8)
EXTCLK
t0
t1
t2
t3
Power Down until next Power Up Cycle
Figure 45. Power Down Sequence
TABLE 35. POWER DOWN SEQUENCE
Definition
Symbol
Min
Typical
Max
Unit
VDD to VDD_IO
t0
0
–
–
ms
VDD_IO to VAA/VAA_PIX
t1
0
–
–
ms
VAA/VAA_PIX to VDD_PLL/DAC
t2
0
–
Power Down until Next Power Up Time
t3
100¹
–
–
ms
–
ms
(1) t3 is required between power down and next power up
time, all decoupling caps from regulators must completely
discharge before next power up.
tFRAME_SYNC
FRAME_SYNC
FRAME_VALID
LINE_VALID
FRMSYNH_FVH
t
Figure 46. FRAME_SYNC to FRAME_VALID/LINE_VALID
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