ASX340AT_16 Datasheet, PDF (28/54 Pages) ON Semiconductor – 1/4‐inch Color CMOS NTSC/PAL Digital Image SOC

ASX340AT
Single READ from Current Location
Figure 18 shows the single READ cycle without writing
the address. The internal address will use the previous
address value written to the register.
Previous Reg Address, N
Reg Address, N+1
N+2
Read Data
Read Data
S
Slave Address
1
A
A
[15:8]
[7:0]
AP
Read Data
Read Data
S
Slave Address
1A
[15:8]
A
[7:0]
AP
Figure 23. Single READ from Current Location
Sequential READ, Start from Random Location
This sequence (Figure 21) starts in the same way as the
single READ from random location (Figure 17). Instead of
generating a no-acknowledge bit after the first byte of data
has been transferred, the master generates an acknowledge
bit and continues to perform byte READs until “L” bytes
have been read.
S
Slave Address 0
Previous Reg Address, N
A Reg Address[15:8]
A Reg Address[7:0]
Reg Address, M
A Sr
Slave Address
1A
Read Data
M+1
A
M+1
M+2
M+3
Read Data
(15:8)
A
Read Data
(7:0)
A
Read Data
(15:8)
A
Read Data
(7:0)
A
M+L−2
M+L−1
M+L
Read Data
(15:8) ^A
Read Data
(7:0)
A
Read Data
(15:8)
A
Read Data
(7:0)
A
P
Figure 24. Sequential READ, Start from Random Location
Sequential READ, Start from Current Location
This sequence (Figure 20) starts in the same way as the
single READ from current location (Figure 18). Instead of
generating a no-acknowledge bit after the first byte of data
has been transferred, the master generates an acknowledge
bit and continues to perform byte reads until “L” bytes have
been read.
Previous Reg Address, N
N+1
N+2
N+L−1
N+L
S Slave Address
Read Data
Read Data
Read Data Read Data Read Data
Read Data
1 A _(15:8)Read AData(7:0)
A
(15:8)
A
(7:0)
A _(15:8)
A _(7:0)
AA
Figure 25. Sequential READ, Start from Current Location
Read Data
(15:8)
A
Read Data
(7:0)
A
P
Read Data
Single Write to Random Location
Figure 21 shows the typical WRITE cycle from the host
to the ASX340AT.The first 2 bytes indicate a 16−bit address
of the internal registers with most−significant byte first. The
following 2 bytes indicate the 16−bit data.
Previous Reg Address, N
S
Slave Address
0A
Reg Address[15:8]
A
Reg Add ress[7:0]
Reg Address, M
A
Wri te Data
M+1
A
AP
Figure 26. Single WRITE to Random Location
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