ASX340AT_16 Datasheet, PDF (27/54 Pages) ON Semiconductor – 1/4‐inch Color CMOS NTSC/PAL Digital Image SOC

ASX340AT
Data Transfer
Data is transferred serially, 8 bits at a time, with the MSB
transmitted first. Each byte of data is followed by an
acknowledge bit or a no-acknowledge bit. This data transfer
mechanism is used for the slave address/data direction byte
and for message bytes.
One data bit is transferred during each SCLK clock period.
SDATA can change when SCLK is low and must be stable
while SCLK is HIGH.
Slave Address/Data Direction Byte
Bits [7:1] of this byte represent the device slave address
and bit [0] indicates the data transfer direction. A “0” in bit
[0] indicates a write, and a “1” indicates a read. The default
slave addresses used by the ASX340AT are 0 x 90 (write
address) and 0 x 91 (read address). Alternate slave addresses
of 0 x BA (write address) and 0 x BB (read address) can be
selected by asserting the SADDR input signal.
Message Byte
Message bytes are used for sending register addresses and
register write data to the slave device and for retrieving
register read data. The protocol used is outside the scope of
the two-wire serial interface specification.
Acknowledge Bit
Each 8-bit data transfer is followed by an acknowledge bit
or a no-acknowledge bit in the SCLK clock period following
the data transfer. The transmitter (which is the master when
writing, or the slave when reading) releases SDATA. The
receiver indicates an acknowledge bit by driving SDATA
LOW. As for data transfers, SDATA can change when SCLK
is LOW and must be stable while SCLK is HIGH.
No-Acknowledge Bit
The no-acknowledge bit is generated when the receiver
does not drive SDATA low during the SCLK clock period
following a data transfer. A no-acknowledge bit is used to
terminate a read sequence.
Stop Condition
A stop condition is defined as a LOW-to-HIGH transition
on SDATA while SCLK is HIGH.
Typical Operation
A typical READ or WRITE sequence begins by the
master generating a start condition on the bus. After the start
condition, the master sends the 8-bit slave address/data
direction byte. The last bit indicates whether the request is
for a READ or a WRITE, where a “0” indicates a WRITE
and a “1” indicates a READ. If the address matches the
address of the slave device, the slave device acknowledges
receipt of the address by generating an acknowledge bit on
the bus.
If the request was a WRITE, the master then transfers the
16-bit register address to which a WRITE will take place.
This transfer takes place as two 8-bit sequences and the slave
sends an acknowledge bit after each sequence to indicate
that the byte has been received. The master will then transfer
the 16-bit data, as two 8-bit sequences and the slave sends an
acknowledge bit after each sequence to indicate that the byte
has been received. The master stops writing by generating
a (re)start or stop condition. If the request was a READ, the
master sends the 8-bit write slave address/data direction byte
and 16-bit register address, just as in the write request. The
master then generates a (re)start condition and the 8-bit read
slave address/data direction byte, and clocks out the register
data, 8 bits at a time. The master generates an acknowledge
bit after each 8-bit transfer. The data transfer is stopped
when the master sends a no-acknowledge bit.
Single READ from Random Location
Figure 17 shows the typical READ cycle of the host to the
ASX340AT. The first two bytes sent by the host are an
internal 16-bit register address. The following 2-byte READ
cycle sends the contents of the registers to host.
Previous Reg Address, N
Reg Address, M
M+1
Read Data
Read Data
S
Slave Address 0 A
Reg Address[15:8] A
Reg Address[7:0] A Sr
Slave Address
1A
A
[15:8]
[7:0]
AP
S = start condition
P = stop condition
Sr = restart condition
A = acknowledge
A = no-acknowledge
slave to master
master to slave
Figure 22. Single READ from Random Location
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