ASX340AT_16 Datasheet, PDF (40/54 Pages) ON Semiconductor – 1/4‐inch Color CMOS NTSC/PAL Digital Image SOC

ASX340AT
TABLE 31. PARALLEL DIGITAL OUTPUT I/O TIMING
(^fEXTCLK = 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V;
VDD_PLL = 2.8 V; VDD_DAC = 2.8 V; Default slew rate)
Signal
EXTCLK
Parameter
Conditions
Min
Typ
f_extclk
6
27
t_{extclk_period}
18.52
37
EXTCLK
PIXCLK¹
Duty cycle
f_pixclk
45
50
6
27
t_{pixclk_period}
18.52
37.04
Duty cycle
45
50
DATA[7:0]
t_{pixclkf_dout}
1.55
–
t_{dout_su}
18
–
t_{dout_ho}
18
–
FV/LV
t_{pixclkf_fvlv}
1.6
–
t_{fvlv_su}
15
–
t_{fvlv_ho}
20
–
Max
54
166.67
55
54
166.67
55
1.9
20
20
3.05
16
21
TABLE 32. SLEW RATE FOR POXCLK AND D_OUT
(^fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V;
VDD_PLL = 2.8 V; VDD_DAC = 2.8 V; T = 25°C; CLOAD = 40 pF)
PIXCLK
DOUT[7:0]
R0x1E [10:8]
Rise Time
Fall Time
R0x1E [2:0]
Rise Time
000
NA
NA
000
15.0
001
NA
NA
001
9.0
010
7.0
6.9
010
6.8
011
5.2
5.0
011
5.2
100
4.0
3.8
100
3.8
101
3.0
2.8
101
3.3
110
2.4
2.2
110
3.0
111
1.9
1.7
111
2.8
Fall Time
13.5
8.5
6.0
4.8
3.5
3.3
3.0
2.8
PIXCLK
trise
90%
10%
t _fall
Unit
MHz
ns
%
MHz
ns
%
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
D OUT
t _rise
t _fall
Figure 42. Slew Rate Timing
www.onsemi.com
40