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AMIS-49587 Datasheet, PDF (6/59 Pages) ON Semiconductor – Power Line Carrier Modem | |||
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AMISâ49587
ELECTRICAL CHARACTERISTICS
DC AND AC CHARACTERISTICS
Oscillator: Pin XIN, XOUT
In production the actual oscillation of the oscillator and duty cycle will not be tested. The production test will be based on the
static parameters and the inversion from XIN to XOUT in order to guarantee the functionality of the oscillator.
Table 7. OSCILLATOR
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Crystal frequency
Duty cycle with quartz connected
(Note 1)
(Note 1)
fCLK
â100 ppm 24 +100 ppm MHz
40
60
%
Startâup time
Maximum Capacitive load on XOUT
Low input threshold voltage
High input threshold voltage
Low output voltage
(Note 1)
XIN used as clock input
XIN used as clock input
XIN used as clock input
XIN used as clock input,
XOUT = 2 mA
Tstartup
CLXOUT
VILXOUT
VIHXOUT
VOLXOUT
0.3 VDD
50
ms
50
pF
V
0.7 VDD
V
0.3
V
High input voltage
XIN used as clock input
VOHXOUT
VDDâ0.3
V
1. For the design of the oscillator crystal parameters have been taken from the data sheet [8]. The series loss resistance for this type of crystal
is maximum 50 W. However the oscillator cell has been designed with some margin for series loss resistance up to 80 W.
Zero Crossing Detector and 50/60Hz PLL: Pin M50HZ_IN
Table 8. ZERO CROSSING DETECTOR AND 50/60HZ PLL
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Maximum peak input current
Maximum average input current
Mains voltage (ms) range
During 1 ms
With protection resistor at
M50HZIN
ImpM50HZIN
â20
ImavgM50HZIN
â2
VMAINS
90
20
mA
2
mA
550
V
Rising threshold level
Falling threshold level
Hysteresis
Lock range for 50 Hz (Note 3)
Lock range for 60 Hz (Note 3)
Lock time (Note 3)
Lock time (Note 3)
Frequency variation without going out of
lock (Note 3)
(Note 2)
(Note 2)
(Note 2)
MAINS_FREQ = 0 (50 Hz)
MAINS_FREQ = 0 (60 Hz)
MAINS_FREQ = 0 (50 Hz)
MAINS_FREQ = 0 (60 Hz)
MAINS_FREQ = 0 (50 Hz)
VIRM50HZIN
VIFM50HZIN
0.9
VHY50HZIN
0.4
Flock50Hz
45
Flock60Hz
54
Tlock50Hz
Tlock60Hz
DF60Hz
1.9
V
V
V
55
Hz
66
Hz
15
s
20
s
0.1
Hz/s
Frequency variation without going out of MAINS_FREQ = 0 (60 Hz)
lock (Note 3)
DF50Hz
0.1
Hz/s
Jitter of CHIP_CLK (Note 3)
JitterCHIP_CLK â25
25
ms
2. Measured relative to VSS.
3. These parameters will not be measured in production since the performance is totally dependent of a digital circuit which will be guaranteed
by the digital test patterns.
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