AMIS-49587 Datasheet, PDF (20/59 Pages) ON Semiconductor – Power Line Carrier Modem

AMIS−49587
(TIC) is modified by the bit 7 of repeater parameter in the
configuration frame :
• bit 7 = 1 −> the TIC value is constant at 10 ms,
• bit 7 = 0 −> the TIC value represents 5 characters
depending on the communication speed (defined by
two local input ports BR0 and BR1).
See Appendix E: timings for Time−out values.
RESET AND LOW POWER
DETAILED SOFTWARE DESCRIPTION
DESCRIPTION
The AMIS−49587 software interface performs the
time−out handling, the error checking, the acknowledgment
and the reception mechanism. The reception mechanism
insures that no collision will occur on the half duplex data
channel. The error checking handles several controls
(checksum frame, length of the frame and command
syntax); an error can provoke repetitions (the base micro has
to choose how many repetitions should be done). The
AMIS−49587 resources are available via local commands,
using the local communication serial interface. All data
exchanged between the AMIS−49587 and the users should
comply with the local communication protocol.
PROTOCOL
The AMIS−49587 and its base micro share a serial bus to
communicate locally. The arbitration of this bus is
performed by the AMIS−49587. The AMIS−49587 can
directly transmit local frame to the base micro, but the base
micro should never transmit local frame without
authorization given by the AMIS−49587 (transmitted in the
status message).
• A Not Set AMIS−49587 only accepts the LTC requests
(Reset_Request, TestMode_Request,
WriteConfig_Request and WriteConfigNew_Request).
• A Master AMIS−49587 accepts the LTC
Reset_Request, WriteConfig_Request and
WriteConfigNew_Request, the DB requests, the MAC
requests and the ISA requests.
• A Slave AMIS−49587 has got two different internal
states. It could react differently with the base micro
requests in function of these states:
♦ Not Synchronized with the mains: it only accepts
the LTC Reset_Request, WriteConfig_Request and
WriteConfigNew_Request, and the DB requests.
♦ Synchronized: it accepts the LTC Reset_Request,
WriteConfig_Request and
WriteConfigNew_Request, the DB requests, the
MAC requests and the ISA requests.
• A Monitor AMIS−49587 accepts the LTC
Reset_Request, WriteConfig_Request and
WriteConfigNew_Request, and the DB requests. When
it is synchronized it supplies the SPY local frames.
Remark: On the AMIS−49587 version 4, the
WriteConfig_Request or WriteConfigNew_Request can be
sent even if the AMIS−49587 is not in the « Not Set » state.
It is not necessary to reset the AMIS−49587 before sending
a WriteConfig_Request any more (NB: this is only available
on AMIS−49587 version 4 and certain conditions must be
respected, see Sections WriteConfig_Request (Tag 31h) and
WriteConfigNew_Request (Tag 71h)).
STATUS MESSAGE
Time Slot Counter in Status Message
The base micro has no information about the availability
of the mains. To solve this problem, the AMIS−49587
supplies a hardware time−slot signal (PRE_SLOT) and a
time−slot counter information included in the status
message. This time−slot counter allows to the base micro to
set its own counter (increased using the hardware time−slot
signal). This time−slot counter is reset at the end of a
communication (end of receiving, end of transmitting or end
of repetition), one time−slot before the first one available for
another communication (see figures below). Following
time−slots are numbered from 1 to 7. The initial value of the
time−slot counter is 7 (”unusable” value). The time−slot
counter takes this initial value at the repetition beginning. To
obtain a coherent value for the time−slot counter, the reading
of the status message must be synchronized with the
hardware pre−slot signal. A time−slot counter value equal to
zero corresponds to the time−slot just before the first one
supposed available (TSC = 1). It informs the base micro that
the AMIS−49587 is ready to accept any MA_Data_Request.
The following draws show how the time slot counter works:
TS i
TS i +1
Sub Frame n
With1 vnv7
SubFrame n
CC = 1
PAUSE
TSC= 7
Time Slot +i 1
Pause
Current Credit
Time Slot counter
Figure 18. Time Slot Legends
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