AMIS-49587 Datasheet, PDF (12/59 Pages) ON Semiconductor – Power Line Carrier Modem

AMIS−49587
FUNCTIONAL DESCRIPTION
The block diagram below represents the main functional
units of the AMIS−49587:
TO Power Amplifier
FROM Line Coupler
TX_ENB
TX_OUT
ALC _IN
Transmitter (S−FSK Modulator)
LP
Filter
D/A
RX_OUT
RX_IN
Receiver (S−FSK Demodulator)
AAF
AGC
A/D
TX_DATA
Transmit Data
& Sine Synthesizer
S−FSK Demodulator
REF_OUT
REF
M50Hz_IN
Clock and Control
Zero
crossing
PLL
Clock Generator
& Timer
OSC
AMIS−49587
Communication Controller
16−bit
ARM
Risc
Core
Serial
Comm.
Interface
I/O ports
Test
Control
POR
Watchdog
Data
RAM
Timer 1 & 2
Program
ROM
Interrupt
Control
TxD
RxD
BR1
BR2
IO[0:2]
TO Application
Micro Controller
JTAG I /F
TEST
RESB
VddA VssA VddD VssD
XIN XOUT
Figure 4. S−FSK Modem AMIS−49587 Block Diagram
Transmitter
The AMIS−49587 Transmitting function block prepares
the communication signal which will be sent on the
transmitting channel during the transmitting phase. This
block is connected to a power amplifier which injects the
output signal on the mains through a coupler.
Receiver
The analog signal coming from the line−coupler is low
pass filtered in order to avoid aliasing during the conversion.
Then the level of the signal is automatically adapted by an
automatic gain control (AGC) block. This operation
maximizes the dynamic range of the incoming signal. The
signal is then converted to its digital representation using
sigma delta modulation. From then on, the processing of the
data is done in a digital way. By using dedicated hardware,
a direct quadrature demodulation is performed. The signal
demodulated in the base band is then low pass filtered to
reduce the noise and reject the image spectrum.
Clock and Control
According to the IEC standard, the frame data is
transmitted at the zero crossing of the mains voltage. In
order to recover the information at the zero crossing, a zero
crossing detection of the mains is performed. A
phase−locked loop (PLL) structure is used in order to allow
a more reliable reconstruction of the synchronization. This
PLL permits as well a safer implementation of the
”repetition with credit” function (also known as chorus
transmission). The clock generator makes use of a precise
quartz oscillator master. The clock signals are then obtained
by the use of a programmed division scheme. The support
circuits are also contained in this block. The support circuits
include the necessary blocks to supply the references
voltages for the AD and DA converters, the biasing currents
and power supply sense cells to generate the right power off
and startup conditions.
24 bit @ 1200 baud
20 ms
Figure 5. Data Stream is in Sync with Zero Crossings
of the Mains
Communication Controller
The Communication Controller block includes the
micro−processor, its peripherals: RAM, ROM, UART,
TIMER, and the Power on reset. The processor uses the
ARM Reduced Instruction Set Computer (RISC)
architecture optimized for IO handling. For most of the
instructions, the machine is able to perform one instruction
per clock cycle. The microcontroller contains the necessary
hardware to implement interrupt mechanisms, timers and is
able to perform byte multiplication over one instruction
cycle. The microcontroller is programmed to handle the
physical layer (chip synchronization), and the MAC layer
conform to IEC 1334−5−1. The program is stored in a
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